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The above algorithm can be optimized in code; however, the important point is to wait for the cancel to
complete because the external interface could have been in the process of reading a value when the
cancel came in, and it must be allowed to complete.
17.4 DMA Operation
The µDMA can be used to achieve maximum transfer rates on the EPI through the NBRFIFO and the
WFIFO. The µDMA has one channel for write and one for read. For writes, the EPI DMA Transmit Count
(EPIDMATXCNT) register is programmed with the total number of transfers by the µDMA. An equivalent
value is programmed into the DMA Channel Control Word (DMACHCTL) register of the uDMA at offset
0x008. A µDMA request is asserted by the EPI WRFIFO when the TXCNT value of the EPIDMATXCNT
register is greater than zero and the WTAV bit field of the EPIWFIFOCNT register is less than the
programmed threshold trigger, WRFIFO, of the EPIFIFOLVL register. The write channel continues to write
data until the TXCNT value in the EPIDMACNT register is zero.
NOTE: When the WRFIFO bit in the EPIFIFOLVL register is set to 0x4 and the application bursts
four words to an empty FIFO, the WRFIFO trigger may or may not de-assert depending on if
all four words were written to the WRFIFO or if the first word was passed immediately to the
function requiring it. Thus, the application may not see the WRRIS bit in the EPIRIS register
clear on a burst of four words.
The non-blocking read channel copies values from the NBRFIFO when the NBRFIFO is at the level
specified by the EPIFIFOLVL register. For non-blocking reads, the start address, the size per transaction,
and the count of elements must be programmed in the µDMA. Note that both non-blocking read register
sets can be used, and they fill the NBRFIFO such that one runs to completion, then the next one starts
(they do not interleave). Using the NBRFIFO provides the best possible transfer rate.
For blocking reads, the µDMA software channel (or another unused channel) is used for memory-to-
memory transfers (or memory to peripheral, where some other peripheral is used). In this situation, the
µDMA stalls until the read is complete and is not able to service another channel until the read is done. As
a result, the arbitration size should normally be programmed to one access at a time. The µDMA controller
can also transfer from and to the NBRFIFO and the WFIFO using the µDMA software channel in memory
mode, however, the µDMA is stalled once the NBRFIFO is empty or the WFIFO is full. Note that when the
µDMA controller is stalled, the core continues operation. See the Micro Direct Memory Access (µDMA)
chapter for more information on configuring the µDMA.
The size of the FIFOs must be taken into consideration when configuring the µDMA to transfer data to and
from the EPI. The arbitration size should be four or less when writing to EPI address space and eight or
less when reading from EPI address space.
17.5 Initialization and Configuration
To enable and initialize the EPI controller, the following steps are necessary:
•
Enable the EPI module using the RCGC1 register (see the System Control chapter).
•
Enable the clock to the appropriate GPIO module via the RCGC2 register. To find out which GPIO port
to enable, see the GPIO chapter.
•
Set the GPIO AFSEL bits for the appropriate pins. To determine which GPIOs to configure, see the
GPIO chapter.
•
Configure the GPIO current level and/or slew rate as specified for the mode selected. See the GPIO
chapter.
•
Configure the PMCn fields in the GPIOPCTL register to assign the EPI signals to the appropriate pins
(see the GPIO chapter)
•
Select the mode for the EPI block to SDRAM, HB8, HB16, or general parallel use, using the MODE
field in the EPI Configuration (EPICFG) register. Set the mode-specific details (if needed) using the
appropriate mode configuration EPI Host Bus Configuration (EPIHBnCFGn) registers for the desired
chip-select configuration. Set the EPI Main Baud Rate (EPIBAUD) and EPI Main Baud Rate 2
(EPIBAUD2) register if the baud rate must be slower than the system clock rate.
•
Configure the address mapping using the EPI Address Map (EPIADDRMAP) register. The selected
SPRUHE8E – October 2012 – Revised November 2019
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DMA Operation
External Peripheral Interface (EPI)
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