Ssisr Register; Ssisr Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

SSI Registers
20.5.2.4 SSISR Register (Offset = Ch) [reset = 3h]
SSISR is shown in
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SSI Status
31 30 29 28
15 14 13 12
Bit Field
31-5 RESERVED
4 BSY
3 RFF
2 RNE
1 TNF
0 TFE
1464
M3 Synchronous Serial Interface (SSI)
Figure 20-13 and described in
Table.
Figure 20-13. SSISR Register
27 26 25
11 10 9
RESERVED
R-0h
Table 20-7. SSISR Register Field Descriptions
Type Reset
R 0h
R 0h
R 0h
R 0h
R 1h
R 1h
Copyright © 2012–2019, Texas Instruments Incorporated
Table 20-7.
24 23 22 21
RESERVED
R-0h
8 7 6 5
Description
Reserved
SSI Busy Bit
Value Description
0 The SSI is idle.
1 The SSI is currently transmitting and/or receiving a frame, or
the transmit FIFO is not empty.
Reset type: PER.RESET
SSI Receive FIFO Full
Value Description
0 The receive FIFO is not full.
1 The receive FIFO is full.
Reset type: PER.RESET
SSI Receive FIFO Not Empty
Value Description
0 The receive FIFO is empty.
1 The receive FIFO is not empty.
Reset type: PER.RESET
SSI Transmit FIFO Not Full
Value Description
0 The transmit FIFO is full.
1 The transmit FIFO is not full.
Reset type: PER.RESET
SSI Transmit FIFO Empty
Value Description
0 The transmit FIFO is not empty.
1 The transmit FIFO is empty.
Reset type: PER.RESET
SPRUHE8E – October 2012 – Revised November 2019
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20 19 18 17
4 3 2 1
BSY RFF RNE TNF
R-0h R-0h R-0h R-1h
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16
0
TFE
R-1h