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Flash Controller Memory Module
5.3.8.1.2 Cache Mode
5.3.8.1.2.1 Program Cache
Flash memory is typically used to store application code. During code execution, instructions are fetched
from sequential memory addresses, except when a discontinuity occurs. Usually, the portion of the code
that resides in sequential addresses makes up the majority of the application code, and is referred to as
linear code. To improve the performance of linear code execution, a flash prefetch-mechanism has been
implemented in FMC. This prefetch mechanism does a look-ahead prefetch on linear address increments
starting from the address of the last program access.
Apart from linear code, in general application codes, there may be several loops wherein a set of
instructions located in sequential addresses are executed repeatedly in a loop, until a condition holds true.
To improve the performance of small loop code execution, an 8-level deep 128-bit wide (8 x 128) direct
mapped program cache has been implemented in the FMC. Whenever instructions in cache are fetched
for CPU processing, the flash prefetch mechanism does a look-ahead prefetch of 128 bits from the next
linear 128-bit aligned address from last address access, and fills the program cache as shown in
82.
Flash cache mode
M
Cortex
U
M3
32-bit
X
CPU
Up to four 32-bit instructions or up to eight 16-bit instructions can reside within a single 128-bit access. For
every 128-bit instruction fetch from the flash bank, it is likely that there are up to eight instructions
(assuming 16-bit instructions) in each level of cache, ready to process through the CPU. During the time it
takes to process these instructions, the flash prefetch mechanism automatically initiates another access to
the flash bank to prefetch the next 128 bits. In this manner, the flash prefetch mechanism works in the
background to keep the cache as full as possible with data corresponding to the next linear address.
Using this technique, the overall efficiency of sequential code execution and small loop code execution
from flash or OTP is improved significantly.
The flash program-cache and prefetch mechanism features are disabled by default. Setting the
PROG_CACHE_EN bit in the FRD_INTF_CTRL register enables this cache mode. This flash prefetch and
cache mechanisms are independent of the CPU pipeline.
540
Internal Memory
Figure 5-82. Flash Cache Mode
8 x 128-bit
Direct mapped
program cache
Instruction fetch
128-bit data cache
Copyright © 2012–2019, Texas Instruments Incorporated
Look ahead prefetch
128-bit prefetch data
Data from DCODE access
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
Figure 5-
Flash and OTP
8-bit
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