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Vector Name (Number)
SVCall (11)
DebugMonitor(12)
Reserved (13)
PendSV (14)
SysTick (15)
GPIOPort-A (16)
Other programmable Interrupts
(17 – 149
As indicated in the table above:
•
On reset, Stack Pointer will point to RAM location 0x20004900. RAM locations 0x20004900-
0x20004000 are reserved for boot ROM.
•
ResetIsr - is the function executed whenever M-Boot ROM is executed after reset.
•
mbrom_nmi_interrupt_handler – is the function executed whenever there is an NMI during boot or as
long as the NVIC base address points to 0x00000000 in M-Boot ROM.
•
mbrom_hard_fault_isr_handler – is the function executed whenever there is a HARD FAULT condition
detected by Cortext-M3 CPU during boot or as long as the NVIC base address points to 0x00000000
in M-Boot ROM.
– NOTE: Memory Management Fault, Bus Fault and Usage Fault exceptions are disabled by default
on reset in Cortex-M3 CPU and so is the case in M-Boot ROM. So if any of these errors occur
during M-Boot ROM execution, they end up triggering a Hard Fault Exception.
•
SysTickIntHandler – is the function used by Ethernet bootloaders for timing during EMAC boot.
•
GpioIntHander – is the function used by the UART bootloader for AutoBaud calculation.
6.5.3 M-Boot ROM Version and Checksum Information
M-Boot ROM contains a version number located at 0x01000258 occupying two bytes. This version is
incremented each time M-Boot ROM code is modified. The next two bytes starting from 0x0100025A
contain the month and year (MM/YY in decimal) that the boot code was released. The next 0x84 bytes
contain a checksum value for the M-Boot ROM. A proprietary checksum algorithm is used on this device
to allow boot ROM to be tested more efficiently. The checksum algorithm used is also embedded in ROM
and will be published along with the device's boot ROM sources.
Address
0x01000258 – 0x01000259
0x0100025A – 0x0100025B
0x0100025C – 0x010002DF
6.5.4 M-Boot ROM RAM Initialization
RAM memories on the master subsystem and control subsystem on Concerto devices must be zero-
initialized before using the RAM for the first time to avoid any ECC and Parity errors. Refer to the Internal
Memory chapter for more details on RAM ECC and Parity.
During the device initialization process, M-Boot ROM reads the MRESC register and if the reset cause is
POR, then all of the master subsystem RAMs are zero-initialized and for all the other reset causes, only
M-Boot ROM stack memory is zero-initialized.
SPRUHE8E – October 2012 – Revised November 2019
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Table 6-2. M-Boot ROM Vector Table (continued)
Vector Address or Location in Boot
ROM
0x0000002C
0x00000030
0x00000034
0x00000038
0X0000003C
0x00000040
0x00000040 - 0x00000254
Copyright © 2012–2019, Texas Instruments Incorporated
Contents (Handler address)
IntDefaultHandler
IntDefaultHandler
Reserved (0x00000000)
IntDefaultHandler
SysTickIntHandler
GPIOIntHandler
IntDefaultHandler
Contents
Revision No = 0x0100
Release Date = 0x1211 ( = 12/2011)
Checksum
ROM Code and Peripheral Booting
M-Boot ROM Description
583
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