Spi Fifo Interrupt Flags And Enable Logic Generation; Spi Interrupt Flag Modes - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Enhanced SPI Module Overview
buffer (TXBUF) of the standard SPI functions as a transition buffer between the transmit FIFO and shift
register. The one-word transmit buffer will be loaded from transmit FIFO only after the last bit of the
shift register is shifted out.
7. Delayed transfer. The rate at which transmit words in the FIFO are transferred to transmit shift register
is programmable. The SPIFFCT register bits (7−0) FFTXDLY7−FFTXDLY0 define the delay between
the word transfer. The delay is defined in number SPI serial clock cycles. The 8-bit register could
define a minimum delay of 0 serial clock cycles and a maximum of 255 serial clock cycles. With zero
delay, the SPI module can transmit data in continuous mode with the FIFO words shifting out back to
back. With the 255 clock delay, the SPI module can transmit data in a maximum delayed mode with
the FIFO words shifting out with a delay of 255 SPI clocks between each words. The programmable
delay facilitates glueless interface to various slow SPI peripherals, such as EEPROMs, ADC, DAC etc.
8. FIFO status bits. Both transmit and receive FIFOs have status bits TXFFST or RXFFST (bits 12− 0)
that define the number of words available in the FIFOs at any time. The transmit FIFO reset bit
TXFIFO and receive reset bit RXFIFO will reset the FIFO pointers to zero when these bits are set to 1.
The FIFOs will resume operation from start once these bits are cleared to zero.
9. Programmable interrupt levels. Both transmit and receive FIFO can generate CPU interrupts. The
interrupt trigger is generated whenever the transmit FIFO status bits TXFFST (bits 12−8) match (less
than or equal to) the interrupt trigger level bits TXFFIL (bits 4−0 ). This provides a programmable
interrupt trigger for transmit and receive sections of the SPI. The default value for these trigger level
bits will be 0x11111 for receive FIFO and 0x00000 for transmit FIFO respectively.
12.1.6.1 SPI Interrupts
Figure 12-7. SPI FIFO Interrupt Flags and Enable Logic Generation
16 x 16-bit FIFO
SPI SOMI
SPI SIMO
SPI Interrupt
FIFO Options Source
SPI without FIFO
Receive overrun
Data receive
Transmit empty
(1)
In non FIFO mode, SPIRXINT is the same as the SPIINT interrupt.
994
C28 Serial Peripheral Interface (SPI)
RX FIFO 15
.
RXFFOVF flag
.
.
RXFFIL
RX FIFO 0
RX BUF
RX_OVRN flag
SPIDAT
SPIINT flag
TX BUF
TX FIFO 0
.
. TXFFIL
.
TX FIFO 15
Table 12-4. SPI Interrupt Flag Modes
Interrupt
Flags
RXOVRN
SPIINT
SPIINT
Copyright © 2012–2019, Texas Instruments Incorporated
RXFFIENA
1
SPIFFENA
0
OVRNINTENA
SPIINTENA
SPIFFENA
TXFFIENA
0
1
Interrupt FIFO Enable
Enables SPIFFENA
OVRNINTENA 0
SPIINTENA 0
SPIINTENA 0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
SPIRXINT
SPITXINT
(1)
Interrupt
line
SPIRXINT
SPIRXINT
SPIRXINT
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