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25.2.4.1.4 Example of SRD Use
Two regions with the same base address overlap. Region one is 128 KB, and region two is 512 KB. To
ensure the attributes from region one apply to the first 128 KB region, configure the SRD field for region
two to 0x03 to disable the first two subregions, as
Base address of both regions
25.2.4.2 MPU Access Permission Attributes
The access permission bits, TEX, S, C, B, AP, and XN of the MPUATTR register, control access to the
corresponding memory region. If an access is made to an area of memory without the required
permissions, then the MPU generates a permission fault.
Table 25-3
shows the encodings for the TEX, C, B, and S access permission bits. All encodings are
shown for completeness, however the current implementation of the Cortex-M3 does not support the
concept of cacheability or shareability. Refer to
MPU for Concerto implementations.
TEX
S
(1)
000b
x
(1)
000
x
000
0
000
1
000
0
000
1
001
0
001
1
(1)
001
x
(1)
001
x
001
0
001
1
(1)
010
x
(1)
010
x
(1)
010
x
(1)
The MPU ignores the value of this bit.
SPRUHE8E – October 2012 – Revised November 2019
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Figure 25-1
Figure 25-1. SRD Use Example
Region 1
Section 25.2.4.2.1
Table 25-3. TEX, S, C, and B Bit Field Encoding
C
B
0
0
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
(1)
1
x
Copyright © 2012–2019, Texas Instruments Incorporated
shows.
Region 2, with
Offset from
subregions
base address
512KB
448KB
384KB
320KB
256KB
192KB
128KB
Disabled subregion
64KB
Disabled subregion
0
for information on programming the
Memory Type
Shareability
Strongly Ordered
Shareable
Device
Shareable
Normal
Not shareable
Normal
Shareable
Normal
Not shareable
Normal
Shareable
Normal
Not shareable
Normal
Shareable
Reserved encoding
-
Reserved encoding
-
Normal
Not shareable
Normal
Shareable
Device
Not shareable
Reserved encoding
-
Reserved encoding
-
Functional Description
Other Attributes
-
-
Outer and inner
write-through. No
write allocate.
Outer and inner
non-cacheable.
-
-
Outer and inner
write-back. Write
and read allocate.
Non-shared
device.
-
-
1641
Cortex-M3 Peripherals
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