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Figure 16-29. DMA Channel Map Assignment (DMACHMAP1) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-36. DMA Channel Map Assignment (DMACHMAP1) Register Field Descriptions
Bit
Field
31-28
27-24
23-20
19-16
15-12
11-8
7-4
3-0
16.7.21 DMA Channel Map Assignment (DMACHMAP2) Register, offset 0x518
Each bit of the DMACHMAP0 register controls the channel assignments for the first, second, and third
mapping.
SPRUHE8E – October 2012 – Revised November 2019
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Value
Description
0
Channel 15 First Assignment
1
Channel 15 Second Assignment
2
Channel 15 Third Assignment
3
Reserved
0
Channel 14 First Assignment
1
Channel 14 Second Assignment
2
Channel 14 Third Assignment
3
Reserved
0
Channel 13 First Assignment
1
Channel 13 Second Assignment
2
Channel 13 Third Assignment
3
Reserved
0
Channel 12 First Assignment
1
Channel 12 Second Assignment
2
Channel 12 Third Assignment
3
Reserved
0
Channel 11 First Assignment
1
Channel 11 Second Assignment
2
Channel 11 Third Assignment
3
Reserved
0
Channel 10 First Assignment
1
Channel 10 Second Assignment
2
Channel 10 Third Assignment
3
Reserved
0
Channel 9 First Assignment
1
Channel 9 Second Assignment
2
Channel 9 Third Assignment
3
Reserved
0
Channel 8 First Assignment
1
Channel 8 Second Assignment
2
Channel 8 Third Assignment
3
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
CHMAP1
R/W
M3 Micro Direct Memory Access ( µDMA)
µDMA Register Descriptions
0
1221
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