Control Subsystem Flash Ecc/Error Log Registers; Ecc Enable Register (Ecc_Enable); Single Error Address Register (Single_Err_Addr); Uncorrectable Error Address Register (Unc_Err_Addr) - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 5-129. Flash Read Interface Control Register (FRD_INTF_CTRL) Field Descriptions

DATA_CACHE_E

5.4.4 Control Subsystem Flash ECC/Error Log Registers

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-130. ECC Enable Register (ECC_ENABLE) Field Descriptions

Figure 5-123. SIngle Error Address Register (SINGLE_ERR_ADDR)

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-131. SIngle Error Address Register (SINGLE_ERR_ADDR) Field Descriptions

Figure 5-124. Uncorrectable Error Address Register (UNC_ERR_ADDR)

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-132. Uncorrectable Error Address Register (UNC_ERR_ADDR) Field Descriptions

SPRUHE8E – October 2012 – Revised November 2019

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Data cache enable.

A value of 0 disables the data cache.

A value of 1 enables the data cache.

Prefetch enable.

A value of 0 disables program cache and prefetch mechanism.

A value of 1 enables program cache and prefetch mechanism.

Figure 5-122. ECC Enable Register (ECC_ENABLE)

ECC enable. A value of 0xA would enable ECC. Any other value would disable ECC.

Single bit error address. Address at which a single bit error occurred, aligned to a 128 bit boundary.

UNC_ERR_ADDR

Uncorrectable error address. Address at which un-correctable error occurred, aligned to a 128 bit

Flash Registers

Internal Memory

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