Texas Instruments Concerto F28M36H53B2 Manuals
Manuals and User Guides for Texas Instruments Concerto F28M36H53B2. We have 1 Texas Instruments Concerto F28M36H53B2 manual available for free PDF download: Technical Reference Manual
Texas Instruments Concerto F28M36H53B2 Technical Reference Manual (1692 pages)
Brand: Texas Instruments
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Category: Microcontrollers
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Size: 11.55 MB
Table of Contents
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Preface79
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WIR Mode93
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PIE Vector Table111
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Safety Features120
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Nmiwds125
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Watchdog Timers125
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Clock Control126
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Power Control126
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Clock Sources127
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Plls128
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CPU-Timers137
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Low Power Modes141
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Security Levels146
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Zone ECSL Status156
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Μcrc Module156
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CRC Polynomials157
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Msgrams158
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CSMKEY1 Register271
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CSMKEY2 Register271
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CSMKEY3 Register271
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CSMCR Register272
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Μcrcres Register276
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Block Diagram306
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GPTM Features306
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Timer Modes308
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DMA Operation312
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16-Bit PWM Mode315
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Register Map315
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Digital I/O Pads351
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Sampling Period390
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Gpioa Mux395
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Gpiob Mux396
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C28 Gpioc Mux397
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C28 Gpiod Mux398
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C28 Gpioe Mux399
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Analog MUX400
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Gpiog Mux400
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Internal Memory462
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RAM Control463
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Extra Wait State465
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Features535
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Flash Tools535
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Flash Cache Mode540
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Introduction579
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Device Boot Flow581
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SPI Loader647
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Random Read652
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Sequential Read652
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Event Filtering742
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Pwm1 )749
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Pwm2 Pwm1749
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Pwm1) )750
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Pwm1 )753
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Pwm2 Pwm1)763
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EQEP Memory Map861
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16-Bit Read894
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16-Bit Write894
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32-Bit Read895
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ADC Trigger895
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ADC Interrupt896
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ADC Registers909
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Comparator939
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Descriptions979
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Descriptions980
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SPI Registers985
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SPI Operation986
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SPI Interrupts988
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Loopback Modes999
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Field Descriptions1004
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Level Is High.)1012
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SCI CPU Interface1017
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Architecture1019
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SCI-A Registers1019
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SCI-B Registers1019
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SCI Interrupt Flags1028
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SCI Registers1031
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SCIA Registers1031
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SCIB Registers1031
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Features1046
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Functional Overview1046
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Clock Generation1047
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Data Validity1048
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Operating Modes1049
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Serial Data Formats1050
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NACK Bit Generation1052
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Arbitration1053
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I2C FIFO Interrupts1055
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I2C Module Registers1056
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Overview1074
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Mcbsp Pins/Signals1075
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Mcbsp Operation1076
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Companding Processes1078
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Clocking1079
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Serial Words1079
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Frame Frequency1081
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Frame Phases1081
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Mcbsp Reception1083
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Mcbsp Transmission1085
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Block Diagram1087
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Types of Errors1093
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2-Partition Mode1102
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Using Two Partitions1102
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SPI Protocol1108
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Clock Stop Mode1109
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Mcbsp Emulation Mode1151
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Mcbsp Registers1155
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Register Summary1156
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Pin Configuration1177
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Interrupt Generation1181
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Error Flags1182
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Mcbsp Mode Selection1183
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Block Diagram1186
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Overview1186
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Μdma Block Diagram1187
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Channel Assignments1188
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Arbitration Size1189
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Priority1189
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Request Types1189
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Request Type Support1190
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Transfer Modes1191
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Peripheral Interface1200
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Software Request1200
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Register Map1206
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Introduction1228
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EPI Block Diagram1229
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Non-Blocking Reads1230
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DMA Operation1231
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SDRAM Mode1232
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Bus Interface Speed1234
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Normal Read Cycle1234
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Write Cycle1235
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Control Pins1236
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Host Bus Mode1236
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SDRAM Write Cycle1236
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Irdy Access Stalls1246
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Host Bus Operation1249
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Alehigh1250
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General-Purpose Mode1252
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Two-Entry FIFO1252
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C28X Access to EPI1260
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Memory Protection1261
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Register Map1262
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CEPIRTWCFG Register1313
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CEPIRTWCNT Register1313
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CEPIRTWPRD Register1314
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CEPISTATUS Register1314
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MEMPROT Register1314
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Block Diagram1317
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Introduction1317
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USB Block Diagram1317
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Operation as a Host1322
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OTG Mode1325
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Actual Bytes Read1327
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DMA Operation1327
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Pin Configuration1328
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Register Map1329
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Usbrxcsrh[15])1385
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Ethernet MAC1418
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Ethernet Frame1419
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SSI Block Diagram1448
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SSI_REGS Registers1457
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SSICR0 Register1459
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SSICR1 Register1461
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SSIDR Register1463
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SSISR Register1464
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SSICPSR Register1465
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SSIIM Register1466
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SSIRIS Register1467
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SSIMIS Register1469
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SSIICR Register1471
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SSIDMACTL Register1472
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SSIPV Register1473
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SSIPP Register1474
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SSIPC Register1475
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Ssipcellid0 Register1484
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Ssipcellid1 Register1485
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Ssipcellid2 Register1486
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Ssipcellid3 Register1487
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UART Character Frame1491
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Irda Data Modulation1492
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LIN Message1493
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Register Map1498
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I2C Block Diagram1522
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CAN Block Diagram1551
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Can_Muxing1554
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Bit Timing1567
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Descriptions1586
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Link Register1610
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Bit-Band Mapping1619
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Data Storage1620
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Interrupts1623
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Faults1629
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SRD Use Example1641
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