Serial Port Loop Back Control (Serploop) Register; Master Subystem: Acib Status (Mcibstatus) Register; Serial Port Loop Back Control (Serploop) Register Field Descriptions; Master Subsystem: Acib Status (Mcibstatus) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Table of Contents

System Control Registers

1.13.2.11 Serial Port Loop Back Control (SERPLOOP) Register

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 1-49. Serial Port Loop Back Control (SERPLOOP) Register Field Descriptions

1.13.2.12 Master Subsystem: ACIB Status (MCIBSTATUS) Register

Figure 1-39. Master Subystem: ACIB Status (MCIBSTATUS) Register

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; x= indeterminate

Table 1-50. Master Subsystem: ACIB Status (MCIBSTATUS) Register Field Descriptions

CIBBUSCLKCNT

System Control and Interrupts

Figure 1-38. Serial Port Loop Back Control (SERPLOOP) Register

UART4-to-SCIA Loopback

UART4 to SCIA connection logic control

Not connected (default on reset)

UART4 connected to SCIA

SSI3-to-SPIA Loopback

SSI3 to SPIA internal connection logic control

Not Connected (default on reset)

SSI3 Connected to SPI-A (SPI-A is in Slave Mode)

SSI3 Connected to SPI-A (SPI-A is in Master Mode)

CIBBUSCLKCNT

8-bit CIBBUSCLK Counter

This free running 8-bit counter is incremented by the CIBBUSCLK. If the counter overflows, it will

rewind to zero and continue counting. This counter is used to indicate if CIBBUSCLK is present.

INTS signal state

Reading this bit will give the current state of the INTS CIB signal at the input.

READY signal state

Reading this bit will give the current state of the READY CIB signal at the input.

Analog System Power Good Status

Reading this bit gives the power state of the Analog Subsystem.

Analog subsystem power not present

Analog subsystem power present

SPRUHE8E – October 2012 – Revised November 2019

Submit Documentation Feedback

Table of Contents