Usb Vbus Droop Control Raw Interrupt Status Register (Usbvdcisc); Usb Vbus Droop Control Raw Interrupt Status Register (Usbvdcisc) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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18.5.58 USB VBUS Droop Control Interrupt Status and Clear Register (USBVDCISC), offset
0x43C
The USB VBUS droop control interrupt status and clear 32-bit register (USBVDCRIS) specifies the
masked interrupt status of the VBUS droop and provides a method to clear the interrupt state.
Mode(s): OTG A or Host
USBVDCISC is shown in
Figure 18-69. USB VBUS Droop Control Raw Interrupt Status Register (USBVDCISC)
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-74. USB VBUS Droop Control Raw Interrupt Status Register (USBVDCISC)
Bit Field Value
31-1 Reserved 0
0 VD
0
1
SPRUHE8E – October 2012 – Revised November 2019
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Figure 18-69 and described in
Reserved
R-0
Field Descriptions
Description
Reserved. Reset is 0x0000.000.
VBUS Droop Interrupt Status and Clear
This bit is cleared by writing a 1. Clearing this bit also clears the VD bit in the USBVDCRIS register.
The VD bits in the USBVDCRIS and USBVDCIM registers are set, providing an interrupt to the interrupt
controller.
No interrupt has occurred or the interrupt is masked.
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Table 18-74.
M3 Universal Serial Bus (USB) Controller
Register Descriptions
1 0
VD
R/W1
C
1409