Ethernet Register Map - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Register Map
19.5 Register Map
Table 19-2 lists the EMAC and MII Management registers. The MAC register addresses given are relative
to the Ethernet base address of 0x4004.8000. The MII Management registers are accessed using the
MACMCTL register. Note that the EMAC clocks must be enabled before the registers can be
programmed. There must be a delay of three system clocks after the Ethernet MAC clock is enabled
before any MAC registers are accessed.
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY layer.
The registers are collectively known as the MII Management registers and are detailed in Section 22.2.4 of
the IEEE 802.3 specification.
are absolute and are written directly to the REGADR field of the Ethernet MAC Management Control
(MACMCTL) register. The format of registers 0 to 15 are defined by the IEEE specification and are
common to all PHY layer implementations. The only variance allowed is for features that may or may not
be supported by a specific PHY implementation. Registers 16 to 31 are vendor-specific registers, used to
support features that are specific to a vendor's PHY implementation.
PHY registers MR0 – MR6 are not located on the microcontroller. These registers are located on IEEE
802.3 compliant Ethernet external PHYs. These registers are defined for software ease of use. See
registers MACMCTL, MACMTXD, and MACMRXD for instructions on how to read and write to the
registers on an external Ethernet PHY.
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040
0x044
MII Management (Accessed through the MACMCTL register)
-
-
1424
M3 Ethernet Media Access Controller (EMAC)
Section 19.7 also lists these MII Management registers. All addresses given
Table 19-2. Ethernet Register Map
Name
MACRIS/MACIACK R/W1C
MACIM
MACRCTL
MACTCTL
MACDATA
MACIA0
MACIA1
MACTHR
MACMCTL
MACMDV
MACMAR
MACMTXD
MACMRXD
MACNP
MACTR
MACTS
-
-
MR0
MR1
Copyright © 2012–2019, Texas Instruments Incorporated
Type Reset
0x0000.0000
R/W 0x0000.007F
R/W 0x0000.0008
R/W 0x0000.0000
R/W 0x0000.0000
R/W 0x0000.0000
R/W 0x0000.0000
R/W 0x0000.003F
R/W 0x0000.0000
R/W 0x0000.0080
R/W 0X0
R/W 0x0000.0000
R/W 0x0000.0000
RO 0x0000.0000
R/W 0x0000.0000
R/W 0x0000.0000
R/W 0x0000.0000
R/W 0x0000.0000
R/W 0x1000
RO 0x7809
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
Description
Ethernet MAC Raw Interrupt
Status/Acknowledge
Ethernet MAC Interrupt Mask
Ethernet MAC Receive Control
Ethernet MAC Transmit
Control
Ethernet MAC Data
Ethernet MAC Individual
Address 0
Ethernet MAC Individual
Address 1
Ethernet MAC Threshold
Ethernet MAC Management
Control
Ethernet MAC Management
Divider
Ethernet MAC Management
Address Register
Ethernet MAC Management
Transmit Data
Ethernet MAC Management
Receive Data
Ethernet MAC Number of
Packets
Ethernet MAC Transmission
Request
Ethernet MAC Timer Support
Reserved
Reserved
Ethernet PHY Management
Register 0 – Control
Ethernet PHY Management
Register 1 – Status
Submit Documentation Feedback