Can Control Register (Can Ctl) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

CAN Control Registers
Bit Name
31-26 Reserved
25 WUBA
24 PDR
23-18 Reserved
17 IE1
16 InitDbg
15 SWR
14 Reserved
13-10 PMD
9 ABO
8 IDS
7 Test
6 CCE
5 DAR
4 Reserved
1582
M3 Controller Area Network (CAN)
Table 23-5. CAN Control Register (CAN CTL) Field Descriptions
Value Description
Reserved
Automatic wake up on bus activity enable bit. This bit is used to enable/disable Automatic wake up
on bus activity, when in local power down mode.
0 No detection of a dominant CAN bus level while in local power down mode.
1 Detection of a dominant CAN bus level while in local power down mode is enabled. On occurrence
of a dominant CAN bus level, the wake up sequence is started.
Note: The CAN message, which initiates the bus activity, cannot be received. This means that the
first message received in power down and automatic wake-up mode, will be lost.
Power Down Mode Request bit. This bit is used to put the CAN module in local power down mode.
0 No application request for local low power down mode. If the application has cleared this bit while
CAN is in power down mode, the INIT bit has to be cleared as well.
1 Power down mode has been requested by application. The CAN module will acknowledge this
mode by setting the PDA bit in Error and Status Register. The local clocks will be turned off by CAN
internal logic.
Reserved
Interrupt line 1 Enable
0 CAN1INT is disabled.
CAN1INT is enabled. Interrupts will assert line CANINT1 to 1; line remains active until pending
interrupts are processed.
Internal init state while debug access
0 Not in debug mode, or debug mode requested but not entered.
1 Debug mode requested and internally entered; the CAN is ready for debug accesses.
Software Reset Enable bit. This bit activates the software reset.
0 Normal operation
1 Module is forced to reset state. This bit will get cleared automatically one clock cycle after execution
of software reset.
Note: To execute software reset the following procedure is necessary:
1. Set INIT bit to shut down CAN communication.
2. Set SWR bit . This bit is EALLOW protected.
Note: This bit is write-protected by the INIT bit.
Reserved
Parity on/off
0101 0101 Parity function disabled
xxxx x(any other value) Parity function enabled
Auto-Bus-On Enable
0 Auto-Bus-On feature is disabled
1 Auto-Bus-On feature is enabled
Interruption Debug Support Enable
0 When Debug mode is requested, CAN will wait for a started transmission or reception to be
completed before entering Debug mode.
1 When Debug mode is requested, CAN will interrupt any transmission or reception, and enter Debug
mode immediately.
Test Mode Enable
0 Disable Test mode (normal operation)
1 Enable Test mode
Configuration Change Enable
0 The CPU has no write access to the configuration registers.
1 The CPU has write access to the configuration registers (when Init bit is set).
Disable Automatic Retransmission
0 Automatic retransmission of "not successful" messages enabled.
1 Automatic retransmission disabled.
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
SPRUHE8E – October 2012 – Revised November 2019
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