Gptm Timer A Mode (Gptmtamr) Register; Gptm Timer A Mode (Gptmtamr) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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This register controls the modes for Timer A when it is used individually. When Timer A and Timer B are
concatenated, this register controls the modes for both Timer A and Timer B, and the contents of
GPTMTBMR are ignored.
Important: Bits in this register should only be changed when the TAEN bit in the GPTMCTL register is
cleared.
31
7
TASNAPS
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-6. GPTM Timer A Mode (GPTMTAMR) Register Field Descriptions
Bit Field
31-8 Reserved
7 TASNAPS
6 TAWOT
5 TAMIE
4 TACDIR
3 TAAMS
2 TACMR
1-0 TAMR
SPRUHE8E – October 2012 – Revised November 2019
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Figure 2-7. GPTM Timer A Mode (GPTMTAMR) Register
6 5
TAWOT TAMIE
R/W-0 R/W-0
Value Description
Reserved
GPTM Timer A Snap-Shot Mode
0 Snap-shot mode is disabled.
1 If Timer A is configured in the periodic mode, the actual free-running value of Timer A is loaded at
the time-out event into the GPTM Timer A (GPTMTAR) register.
GPTM Timer A Wait-on-Trigger
0 Timer A begins counting as soon as it is enabled.
1 If Timer A is enabled (TAEN is set in the GPTMCTL register), Timer A does not begin counting until
it receives a trigger from the timer in the previous position in the daisy chain, see
function is valid for both one-shot and periodic modes.
This bit must be clear for GP Timer Module 0, Timer A.
GPTM Timer A Match Interrupt Enable
0 The match interrupt is disabled
1 An interrupt is generated when the match value in the GPTMTAMATCHR register is reached in the
one-shot and periodic modes.
GPTM Timer A Count Direction
0 The timer counts down
1 When in one-shot or periodic mode, the timer counts up. When counting up, the timer starts from a
value of 0x0.
GPTM Timer A Alternate Mode Select
0 Capture mode is enabled.
0 PWM mode is enabled.
Note: To enable PWM mode, you must also clear the TACMR bit and configure the TAMR field to
0x1 or 0x2.
GPTM Timer A Capture Mode
0 Edge-Count mode
1 Edge-Time mode
GPTM Timer A Mode. The timer mode is based on the timer configuration defined by bits 2:0 in the
GPTMCFG register
0x0 Reserved
0x1 One-Shot Timer mode
0x2 Periodic Timer mode
0x3 Capture mode
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4 3
TACDIR TAAMS
R/W-0 R/W-0
Register Descriptions
2 1
TACMR TAMR
R/W-0 R/W-0
Figure 2-2. This
M3 General-Purpose Timers
8
0
317