I2C Master Data (I2Cmdr) Register; I2C Master Timer Period (I2Cmtpr) Register; I2C Master Data (I2Cmdr) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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22.6.3 I2C Master Data (I2CMDR), offset 0x008
Important: This register is read-sensitive. See the register description for details.
The I2C Master Data (I2CMDR) register contains the data to be transmitted when in the Master Transmit
state and the data received when in the Master Receive state. It is shown and described in the figure and
table below.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-8 Reserved
7-0 DATA
22.6.4 I2C Master Timer Period (I2CMTPR), offset 0x00C
Th I2C master timer period (I2CMTPR) register specifies the period of the SCL clock. It is shown and
described in the figure and table below.
Take care not to set bit 7 when accessing this register as unpredictable
behavior can occur.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-7 Reserved
6-0 TPR
SPRUHE8E – October 2012 – Revised November 2019
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Figure 22-17. I2C Master Data (I2CMDR) Register
Reserved
R-0
Table 22-7. I2C Master Data (I2CMDR) Register Field Descriptions
Value Description
Reserved
00h Data Transferred
Data transferred during transaction.
Figure 22-18. I2C Master Timer Period (I2CMTPR) Register
Reserved
R-0
Table 22-8. I2C Master Data (I2CMDR) Register Field Descriptions
Value Description
Reserved
1h SCL Clock Period
SCL_PRD = 2×(1 + TPR)×(SCL_LP + SCL_HP)×CLK_PRD where:
SCL_PRD is the SCL line period (I2C clock).
TPR is the Timer Period register value (range of 1 to 127).
SCL_LP is the SCL Low period (fixed at 6).
SCL_HP is the SCL High period (fixed at 4).
CLK_PRD is the system clock period in ns.
Copyright © 2012–2019, Texas Instruments Incorporated
CAUTION
M3 Inter-Integrated Circuit (I2C) Interface
Register Descriptions
8 7
DATA
R/W-0
7 6
TPR
R/W-0
0
0
1541