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Note that the CTOMIPCSET registers are write-only by the C28x and will always read back as 0. The
C28x should read the CTOMIPCFLG register to see pending requests. The CTOMIPCFLG and
CTOMIPCSTS registers are read-only and will always reflect the current status of the corresponding IPC
flag whether it has been requested or cleared. The CTOMIPCCLR and CTOMIPCACK bits are write-only
and will always read back as 0. In the event of simultaneous write accesses to the same bits of the
CTOMIPCACK and CTOMIPCSET register, the M3 CPU trying to clear and the C28 CPU trying to set, the
C28 CPU receives priority.
1.12.5 Examples for Software IPC Procedure
The below are given suggested examples of the sequence to be followed in software for IPC.
1.12.5.1 IPC With Interrupts
Below is an example procedure for IPC usage when the M3 CPU wants to get some information from the
C28x using MTOCIPCINT1:
•
The M3 writes a '1' in bit 0 of the MTOCIPCSET register and this generates the MTOCIPCINT0 to the
C28x through the PIE.
•
Bit 0 in the MTOCIPCFLG and MTOCIPCSTS registers get set. The C28x services the interrupt and in
the corresponding ISR, the C28x loads the pre-defined information in the shared RAMs or CTOM-
message RAM (user application has to define the ISR functionality).
•
The C28x clears this MTOCIPC request by writing a '1' to bit 0 of the MTOCIPCACK register at the
end of the ISR.
•
The M3 polls the status of bit 0 in the MTOCIPCFLG register and until the status is '1', it understands
that the C28x CPU has not serviced the interrupt. When the status becomes '0', it understands that the
C28x CPU has serviced the interrupt and reads the RAM from the predefined location and gathers the
requested information.
1.12.5.2 IPC With Flags
Below is an example procedure for IPC usage when the C28x CPU wants to communicate a message to
the M3 about a shared resource using CTOMIPC-flag 5:
•
The C28x writes a '1' to bit 5 of the CTOMIPCSET register to indicate that the M3 can go ahead and
use a particular resource as the C28x is done with using that resource. (In user application software,
IPC flag 6 will be tied to a particular resource and task.)
•
When the M3 wants to use this resource, it will read bit 5 of the CTOMIPCSTS register. When the M3
reads bit 5 of the CTOMIPCSTS register as a '1', it uses shared resource tied to IPC flag 6 in the pre-
defined manner.
•
After completing the task using the shared resource tied with IPC5, the M3 CPU will clear the flag by
writing '1' to bit 5 of CTOMIPCACK.
•
When bit 5 of the CTOMIPCFLG register is a '1' and the flag is not yet cleared by the M3 CPU, if the
C28 CPU reads bit 5 of the CTOMIPCFLG register, the C28x reads it as a '1'. When the flag has been
cleared by the M3, bit 5 of the CTOMIPCFLG will read '0'. Based on this, C28 software proceeds
accordingly for its task.
1.12.6 IPC Message Registers
IPC message registers provide a simple and flexible way for the master subsystem and control subsystem
to send messages between them. There are four dedicated IPC message registers on both subsystems.
There is not any specific hardware definition for the usage of these registers. The user's application
software has to define the usage of these registers. These registers can be used like mailboxes to send
messages back and forth between the two subsystems when the software cannot use memories for inter
processor communication. IPC Message registers on each of the subsystems are accessible by other
subsystems.
IPC Message registers that the master subsystem can use to convey a message to the control subsystem
are given in
Table
SPRUHE8E – October 2012 – Revised November 2019
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1-36.
Copyright © 2012–2019, Texas Instruments Incorporated
Inter Processor Communications (IPC)
System Control and Interrupts
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