Host Bus Operation; Host-Bus Read Cycle, Mode = 0X1, Wrhigh = 0, Rdhigh = 0, Alehigh = 1 - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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which can be read more quickly by only changing the address (and not using RD/OE strobing). In this
sub-mode, reads are performed by keeping the read mode selected (output enable is asserted) and
then changing the address pins. The data pins are changed by the SRAM after the address pins
change. For example, to read data from address 0x100 and then 0x101, the EPI controller asserts the
output-enable signal and then configures the address pins to 0x100; the EPI controller then captures
what is on the data pins and increments A0 to 1 (so the address is now 0x101); the EPI controller then
captures what is on the data pins. Note that this mode consumes higher power because the SRAM
must continuously drive the data pins. This mode is not practical in HB16 mode for normal SRAMs
because there are generally not enough address bits available. Writes are not permitted in this mode.
• FIFO mode uses 8 or 16 bits of data, removes ALE and address pins and optionally adds external
XFIFO FULL/EMPTY flag inputs. This scheme is used by many devices, such as radios,
communication devices (including USB2 devices), and some FPGA configurations (FIFO through block
RAM). This sub-mode provides the data side of the normal Host-Bus interface, but is paced by the
FIFO control signals. It is important to consider that the XFIFO FULL/EMPTY control signals may stall
the interface and could have an impact on blocking read latency from the processor or μDMA.
The WORD bit in the EPIHBnCFG2 register can be set to use memory more efficiently. By default, the EPI
controller uses data bits [7:0] for Host-Bus 8 accesses or bits [15:0] for Host-Bus 16 accesses. When the
WORD bit is set, the EPI controller can automatically route bytes of data onto the correct byte lanes such
that bytes or words of data can be transferred on the correct byte or half-word bits on the entire bus. For
example, the most significant byte of data will be transferred on bits [31:28] in host-bus 8 mode and the
most significant word of data will be transferred on bits [31:16] of Host-Bus 16 mode. In addition, for the
three modes above (1, 2, 4) that the Host-Bus 16 mode supports, byte select signals can be optionally
implemented by setting the BSEL bit in the EPIHB16CFG register.
Note: Byte accesses should not be attempted if the BSEL bit has not been enabled in Host-Bus 16 mode.
See your device-specific data manual's EPI Electricals section for timing details for the Host-Bus mode.

17.7.4 Host Bus Operation

Bus operation is the same in Host-Bus 8 and Host-Bus 16 modes and is asynchronous. Timing diagrams
show both ALE and CS operation. The optional HB16 byte select signals have the same timing as the
address signals. If wait states are required in the bus access, they can be inserted during the data phase
of the access using the WRWS and RDWS bits in the EPIHBnCFG2 register. Each wait state adds 2 EPI
clock cycles to the duration of the WR or RD strobe. During idle cycles, the address and muxed address
data signals maintain the state of the last cycle.
Figure 17-8 shows a basic Host-Bus read cycle.
these figures show address and data signals in the non-multiplexed mode (MODE field ix 0x1 in the
EPIHBnCFG register).
Figure 17-8. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0, ALEHIGH = 1
ALE
( )
EPI0S30
CS
(EPI0S30)
WR
( )
EPI0S29
RD/OE
( )
EPI0S28
BSEL0/
a
BSEL1
Address
Data
a
BSEL0 and BSEL1 are available in Host-Bus16 mode only .
SPRUHE8E – October 2012 – Revised November 2019
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Figure 17-9
Copyright © 2012–2019, Texas Instruments Incorporated
shows a basic Host-Bus write cycle. Both of
Data
External Peripheral Interface (EPI)
Host Bus Mode
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