Peripherals Register Map - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 25-6. Memory Region Attributes for Concerto Microcontrollers (continued)
Memory Region
External SRAM
Peripherals
In current Concerto microcontroller implementations, the shareability and cache policy attributes do not
affect the system behavior. However, using these settings for the MPU regions can make the application
code more portable. The values given are for typical situations.
25.2.4.3 MPU Mismatch
When an access violates the MPU permissions, the processor generates a memory management fault
(see the Cortex-M3 Processor chapter for more information). The MFAULTSTAT register indicates the
cause of the fault.
25.3 Register Map
Table 25-7 lists the Cortex-M3 Peripheral SysTick, NVIC, SCB, and MPU registers. The offset listed is a
hexadecimal increment to the register's address, relative to the Core Peripherals base address of
0xE000.E000 (ending address of 0xE000.EFFF).
Note
Register spaces that are not used are reserved for future or internal use. Software should not modify any
reserved memory address.
Offset Name
0x010 STCTRL
0x014 STRELOAD
0x018 STCURRENT
Nested Vectored Interrupt Controller (NVIC) Registers
0x100 EN0
0x104 EN1
0x108 EN2
0x10C EN3
0x110 EN4
0x180 DIS0
0x184 DIS1
0x188 DIS2
0x18C DIS3
0x190 DIS4
0x200 PEND0
0x204 PEND1
0x208 PEND2
0x20C PEND3
0x210 PEND4
0x280 UNPEND0
0x284 UNPEND1
SPRUHE8E – October 2012 – Revised November 2019
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TEX S
000b 1
000b 1
Table 25-7. Peripherals Register Map
Type
R/W
R/W
R/WC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Copyright © 2012–2019, Texas Instruments Incorporated
C B
1 1
0 1
Reset
0x0000.0004
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
Register Map
Memory Type and
Attributes
Normal memory,
shareable, write-
back, write-allocate
Device memory,
shareable
Description
SysTick Control and Status
Register
SysTick Reload Value Register
SysTick Current Value
Register
Interrupt 0-31 Set Enable
Interrupt 32-63 Set Enable
Interrupt 64-95 Set Enable
Interrupt 96-127 Set Enable
Interrupt 128-133 Set Enable
Interrupt 0-31 Clear Enable
Interrupt 32-63 Clear Enable
Interrupt 64-95 Clear Enable
Interrupt 96-127 Clear Enable
Interrupt 128-133 Clear Enable
Interrupt 0-31 Set Pending
Interrupt 32-63 Set Pending
Interrupt 64-95 Set Pending
Interrupt 96-127 Set Pending
Interrupt 128-133 Set Pending
Interrupt 0-31 Clear Pending
Interrupt 32-63 Clear Pending
1643
Cortex-M3 Peripherals