Gptm Masked Interrupt Status (Gptmmis) Register, Offset 0X020; Gptm Masked Interrupt Status (Gptmmis) Register - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Register Descriptions
Table 2-10. GPTM Raw Interrupt Status (GPTMRIS) Register Field Descriptions (continued)
Bit Field
10 CBERIS
9 CBMRIS
8 TBTORIS
7-5 Reserved
4 TAMRIS
3 RTCRIS
2 CAERIS
1 CAMRIS
0 TATORIS

2.6.7 GPTM Masked Interrupt Status (GPTMMIS) Register, offset 0x020

The GPTM Masked Interrupt Status (GPTMMIS) register shows the state of the GPTM's controller-level
interrupt. If an interrupt is unmasked in GPTMIMR, and there is an event that causes the interrupt to be
asserted, the corresponding bit is set in this register. All bits are cleared by writing a 1 to the
corresponding bit in GPTMICR.
31
15
Reserved
7 6
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
322
M3 General-Purpose Timers
Value Description
GPTM Capture B Event Raw Interrupt
0 The Capture B event has not occurred.
1 The Capture B event has occurred.
GPTM Capture B Match Raw Interrupt
0 The Capture B match has not occurred.
1 The Capture B match has occurred.
This bit is cleared by writing a 1 to the CBMCINT bit in the GPTMICR register
GPTM Timer B Time-Out Raw Interrupt
0 Timer B has not timed out.
1 ITimer B has timed out.
GPTM Timer A Mode Match Raw Interrupt
0 The match value has not been reached.
1 The TAMIE bit is set in the GPTMTAMR register, and the match value in the GPTMTAMATCHR
register has been reached when in the one-shot and periodic modes.
This bit is cleared by writing a 1 to the TAMCINT bit in the GPTMICR register
GPTM RTC Raw Interrupt
0 The RTC event has not occurred
1 The RTC event has occurred
GPTM Capture A Event Raw Interrupt
0 The Capture A event has not occurred.
1 The Capture A event has occurred.
GPTM Capture A Match Raw Interrupt
0 The Capture A match has not occurred.
1 The Capture A match has occurred.
This bit is cleared by writing a 1 to the CAMCINT bit in the GPTMICR register.
GPTM Timer A Time-Out Raw Interrupt
0 Timer A has not timed out.
1 Timer A has timed out.
This bit is cleared by writing a 1 to the TATOCINT bit in the GPTMICR register.
Figure 2-12. GPTM Masked Interrupt Status (GPTMMIS) Register
12
R-0
5 4
TAMMIS
R-0
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Reserved
R-0
11 10
TBMMIS CBEMIS
R-0 R-0
3 2
RTCMIS CAEMIS
R-0 R-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
16
9 8
CBMMIS TBTOMIS
R-0 R-0
1 0
CAMMIS TATOMIS
R-0 R-0
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