Wir Mode; Control Subsystem Resets, Signals And Effects - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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No. Reset Source
1 POR
2 XRS
3 MWDT0 reset
4 MWDT1 reset
5 MNMIWD
6 Master Software reset
7 Master Debugger Reset
C28 Debugger Reset
8
(SYSRS)
9 C28 NMIWD Reset
1.3.2.2.1 Reset Handling in Control Subsystem Boot ROM
The C28x CPU core of the control subsystem starts executing code from the reset vector located at
0x3FFFC0. ROM is mapped to this location of the memory map, and this location points to the reset
vector located in ROM. The ROM associated with the control subsystem will be referred to as C-Boot
ROM in this document.
Whenever the control subsystem is reset because of any of the reset sources as mentioned in
the CPU will start executing code from C-Boot ROM. C-Boot ROM uses the first 0x180 locations of M0
RAM for its execution stack so on start up, C-Boot ROM will ZERO-INIT the entire M0 RAM. This is done
to clear unwanted RAM ECC errors which might pop-up by default on a reset or power-up. It is up to the
application to reset other RAM(s) of the control subsystem. C-Boot ROM then enables the PIE and installs
interrupt handlers for handling IPC communication from the master subsystem and enters IDLE mode. C-
Boot ROM wakes up if there is an IPC interrupt from the master subsystem, handles the IPC
communication, and goes back to IDLE mode. Please refer to the Boot ROM chapter for more details on
the C-Boot ROM procedure and supported IPC communication.
If there is an NMI during the execution time of C-Boot ROM (except for a Missing Clock NMI), C-Boot
ROM acknowledges the NMI, sends an IPC to the master subsystem, updates the status in
CTOMBOOTSTS register, and enters a while(1) loop waiting for the master subsystem to handle the NMI
error condition. A missing clock NMI is triggered to both the master and control subsystems, but in this
event, the control subsystem will acknowledge this NMI and return back to what it was doing before the
interrupt.
Refer to Section 1.5.6.1
In short, the control subsystem acts as a slave to the master subsystem by going to IDLE mode and
waiting for the master subsystem's command on how to proceed further.
1.4

WIR Mode

This device supports a wait-in-reset mode which is primarily used to hold the master and control
subsystem CPU cores in a known active state prior to initiating a Flash programming procedure. This is
especially important on "fresh" devices where the Flash is not programmed. This mode is also important in
avoiding accidently tripping security mechanisms before the debugger has had a chance to connect to the
CPUs.
Both the master and control subsystems each have a WIR mode register; MWIR for the master subsystem
WIR mode register and CWIR for the control subsystem WIR mode register. These registers are read by
M-Boot ROM and C-Boot ROM respectively, each time boot ROM is run after any kind of reset.
Both MWIR and CWIR registers are latched in with the state of the same EMU0 and EMU1 pins on XRS,
or whenever the SAMPLE bit (bit 2) is set in the respective WIR mode register. See the MWIR and CWIR
register descriptions in the System Control Registers section for more details.
Table 1-7 shows which of the different possible values on EMU0 and EMU1 pins can put the device in
WIR mode.
SPRUHE8E – October 2012 – Revised November 2019
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Table 1-6. Control Subsystem Resets, Signals and Effects
C28x Core Reset
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
for more details on CNMI sources and how C-Boot ROM handles each NMI.
Copyright © 2012–2019, Texas Instruments Incorporated
JTAG Reset Control Subsystem
Reset
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
No Yes
No Yes
WIR Mode
Control Subsystem
Held in Reset
Yes
Yes
Yes
Yes
Yes
No
No
No
No
Table
System Control and Interrupts
1-6,
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