Event-Trigger Interrupt Pre-Scale Register (Etintps); Event-Trigger Interrupt Pre-Scale Register (Etintps) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Registers
Table 7-85. Event-Trigger Prescale Register (ETPS) Field Descriptions (continued)
Bit Field
1-0 INTPRD
Figure 7-134. Event-Trigger Interrupt Pre-Scale Register (ETINTPS)
15
7
INTCNT2
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-86. Event-Trigger Interrupt Pre-Scale Register (ETINTPS) Field Descriptions
Bit Field
15-8 Reserved
7-4 INTCNT2
820
C28 Enhanced Pulse Width Modulator (ePWM) Module
Value Description
ePWM Interrupt (EPWMx_INT) Period Select
These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt
is generated. To be generated, the interrupt must be enabled (ETSEL[INT] = 1). If the interrupt
status flag is set from a previous interrupt (ETFLG[INT] = 1) then no interrupt will be generated until
the flag is cleared via the ETCLR[INT] bit. This allows for one interrupt to be pending while another
is still being serviced. Once the interrupt is generated, the ETPS[INTCNT] bits will automatically be
cleared.
Writing to the INTPRD bits in different situations will cause the following results:
• Writing an INTPRD value that is GREATER or equal to the current counter value will reset the
INTCNT = 0
• Writing an INTPRD value that is equal to the current counter value will trigger an interrupt if it is
enabled and the status flag is cleared (and INTCNT will also be cleared to 0)
• Writing an INTPRD value that is LESS than the current counter value will result in undefined
behavior (that is, INTCNT stops counting because INTPRD is below INTCNT, and interrupt will
never fire).
If a counter event occurs at the same instant as a new zero or non-zero INTPRD value is written,
the counter is incremented.
00 Disable the interrupt event counter. No interrupt will be generated and ETFRC[INT] is ignored.
01 Generate an interrupt on the first event INTCNT = 01 (first event)
10 Generate interrupt on ETPS[INTCNT] = 1,0 (second event)
11 Generate interrupt on ETPS[INTCNT] = 1,1 (third event)
4
R-0:0
Value Description
Reserved
EPWMxINT Counter 2
When ETPS[INTPSSEL]=1, these bits indicate how many selected events have occurred:
0000 No events
0001 1 event
0010 2 events
0011 3 events
0100 4 events
. . . . . .
1111 15 events
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
3
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
8
0
INTPRD2
R/W-0:0
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