Ethernet Mac Management Divider (Macmdv) Register; Ethernet Mac Management Address Register (Macmar); Ethernet Mac Management Transmit Data (Macmtxd) Register; Ethernet Mac Management Divider (Macmdv) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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19.6.10 Ethernet MAC Management Divider (MACMDV) Register, offset 0x024
The Ethernet MAC Management Divider (MACMDV) register enables software to set the clock divider for
the Management Data Clock (MDC). This clock is used to synchronize read and write transactions
between the system and the MII Management registers. The frequency of the MDC clock can be
calculated from the following formula:
F
=
F
mdc
(
×
2 MACMDV
The clock divider must be written with a value that ensures that the MDC clock does not exceed a
frequency of 2.5 MHz.
Figure 19-14. Ethernet MAC Management Divider (MACMDV) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-13. Ethernet MAC Management Divider (MACMDV) Register Field Descriptions
Bit Field
31-8 Reserved
7-0 DIV
19.6.11 Ethernet MAC Management Address Register (MACMAR), offset 0x028
The Ethernet MAC Management Address register (MACMAR) allows software to choose the address of
the PHY from the next MII management register transaction. Because there is currently only a single PHY
in Fury, the PHYADR bits should not be written and left at 0x00.
Figure 19-15. Ethernet MAC Management Address Register (MACMAR)
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-14. Ethernet MAC Management Address Register (MACMAR) Field Descriptions
Bit Field
31-5 Reserved
4-0 PHYADR
19.6.12 Ethernet MAC Management Transmit Data (MACMTXD) Register, offset 0x02C
The Ethernet MAC Management Transmit Data (MACMTXD) register holds the next value to be written to
the MII Management registers.
Figure 19-16. Ethernet MAC Management Transmit Data (MACMTXD) Register
31
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUHE8E – October 2012 – Revised November 2019
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ipclk
)
+
1
Reserved
R-0
Value Description
Reserved
Clock divider
80h The DIV bits are used to set the clock divider for the MDC clock used to transmit data between the
MAC and external PHY layers.
Reserved
R-0
Value Description
Reserved
0000h The PHYADR bits represent the address of the PHY that will be accessed in the next MII
management transaction.
R-0
Copyright © 2012–2019, Texas Instruments Incorporated
16 15
M3 Ethernet Media Access Controller (EMAC)
Ethernet MAC Register Descriptions
8 7
DIV
R/W-0
5 4
PHYADR
R/W-0
MDTX
R/W-0
0
0
0
1435