Serial Peripheral Interface Module Block Diagram - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Enhanced SPI Module Overview
Figure 12-2. Serial Peripheral Interface Module Block Diagram
SPIFFENA
SPIFFTX.14
RX FIFO registers
SPIRXBUF
RX FIFO _0
RX FIFO _1
−−−−−
RX FIFO _15
16
SPIRXBUF
Buffer Register
TX FIFO registers
SPITXBUF
TX FIFO _15
−−−−−
TX FIFO _1
TX FIFO _0
SPITXBUF
Buffer Register
16
SPIDAT
Data Register
SPIDAT.15 − 0
Talk
SPICTL.1
State Control
SPI Char SPICCR.3 − 0
3 2
SPI Bit Rate
LSPCLK
SPIBRR.6 − 0
6 5 4
A SPISTE of a slave device is driven low by the master.
984
C28 Serial Peripheral Interface (SPI)
Receiver
Overrun Flag
SPISTS.7
RX FIFO Interrupt
SPIFFOVF FLAG
SPIFFRX.15
TX FIFO Interrupt
16
SPI INT FLAG
SPISTS.6
16
M
S SW1
M
S
SW2
S
1 0
M
3 2 1 0
Copyright © 2012–2019, Texas Instruments Incorporated
Overrun
INT ENA
SPICTL.4
RX Interrupt
Logic
TX Interrupt
Logic
SPI INT
ENA
SPICTL.0
M
S
M
S
Master/Slave
SPICTL.2
SW3
Clock
S Polarity
SPICCR.6
M
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
SPINT / SPIRXINT
To CPU
SPITX / SPITXINT
SPISIMO
SPISOMI
†
SPISTE
*
Clock
Phase
SPICTL.3 SPICLK
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