Dma Channel Map Assignment (Dmachmap1) Register, Offset 0X514; Dma Channel Map Assignment (Dmachmap0) Register; Dma Channel Map Assignment (Dmachmap0) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

µDMA Register Descriptions
Figure 16-28. DMA Channel Map Assignment (DMACHMAP0) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-35. DMA Channel Map Assignment (DMACHMAP0) Register Field Descriptions
Bit Field
31-28
27-24
23-20
19-16
15-12
11-8
7-4
3-0

16.7.20 DMA Channel Map Assignment (DMACHMAP1) Register, offset 0x514

Each bit of the DMACHMAP0 register controls the channel assignments for the first, second, and third
mapping.
1220
M3 Micro Direct Memory Access ( µDMA)
Value Description
0 Channel 7 First Assignment
1 Channel 7 Second Assignment
2 Channel 7 Third Assignment
3 Reserved
0 Channel 6 First Assignment
1 Channel 6 Second Assignment
2 Channel 6 Third Assignment
3 Reserved
0 Channel 5 First Assignment
1 Channel 5 Second Assignment
2 Channel 5 Third Assignment
3 Reserved
0 Channel 4 First Assignment
1 Channel 4 Second Assignment
2 Channel 4 Third Assignment
3 Reserved
0 Channel 3 First Assignment
1 Channel 3 Second Assignment
2 Channel 3 Third Assignment
3 Reserved
0 Channel 2 First Assignment
1 Channel 2 Second Assignment
2 Channel 2 Third Assignment
3 Reserved
0 Channel 1 First Assignment
1 Channel 1 Second Assignment
2 Channel 1 Third Assignment
3 Reserved
0 Channel 0 First Assignment
1 Channel 0 Second Assignment
2 Channel 0 Third Assignment
3 Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
CHMAP0
R/W
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
0
Submit Documentation Feedback