I2C Master Configuration (I2Cmcr) Register; I2C Master Configuration (I2Cmcr) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Register Descriptions
22.6.9 I2C Master Configuration (I2CMCR), offset 0x020
The I2C Master Configuration (I2CMCR) register configures the mode (master or slave) and sets the
interface for test mode loopback. It is shown in the figure and table below.
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-13. I2C Master Configuration (I2CMCR) Register Field Descriptions
Bit Field
31-6 Reserved
5 SFE
4 MFE
3-1 Reserved
0 LPBK
1544
M3 Inter-Integrated Circuit (I2C) Interface
Figure 22-23. I2C Master Configuration (I2CMCR) Register
Reserved
R-0
Value Description
Reserved
I2C Slave Function Enable
0 Slave mode is disabled.
1 Slave mode is enabled.
I2C Master Function Enable
0 Master mode is disabled.
1 Master mode is enabled.
Reserved
I2C Loopback
0 Normal operation
1 The controller in a test mode loopback configuration.
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Reserved
R-0
6 5
SFE
R/W-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
4 3 1
MFE Reserved
R/W-0 R-0 R/W-0
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16
0
LPBK