Data High Test Register (Fdatah_Test); Data Low Test Register (Fdatal_Test); Ecc Test Address Register (Faddr_Test); Ecc Test Register (Fecc_Test) - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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5.4.4.11 Data High Test Register (FDATAH_TEST)

31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-140. Data High Test Register (FDATAH_TEST) Field Descriptions
Bit Field
31-0 FDATAH

5.4.4.12 Data Low Test Register (FDATAL_TEST)

31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-141. Data Low Test Register (FDATAL_TEST) Field Descriptions
Bit Field
31-0 FDATAL

5.4.4.13 ECC Test Address Register (FADDR_TEST)

31
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-142. ECC Test Address Register (FADDR_TEST) Field Descriptions
Bit Field
31-24 Reserved
23-3 ADDR
2-0 Reserved

5.4.4.14 ECC Test Register (FECC_TEST)

31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUHE8E – October 2012 – Revised November 2019
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Figure 5-132. Data High Test Register (FDATAH_TEST)
Value Description
High double word of selected 64-bit data. User-configurable bits 63:32 of the selected data blocks
in ECC test mode.
Figure 5-133. Data Low Test Register (FDATAL_TEST)
Value Description
Low double word of selected 64-bit data. User-configurable bits 31:0 of the selected data blocks in
ECC test mode.
Figure 5-134. ECC Test Address Register (FADDR_TEST)
24 23
Value Description
Reserved
Address for selected 64-bit data. User-configurable address bits of the selected data in
ECC test mode. Left-shift the address by one bit (to provide byte address) and ignore
the three least significant bits of the address and write the remaining address bits in
this field.
Reserved
Figure 5-135. ECC Test Register (FECC_TEST)
Reserved
R-0
Copyright © 2012–2019, Texas Instruments Incorporated
FDATAH
R/W-0
FDATAL
R/W-0
ADDR
R/W-0
Flash Registers
3 2
Reserved
R-0
8 7
ECC
R/W-0
Internal Memory
0
0
0
0
575