Clock Stop Mode; Bits Used To Enable And Configure The Clock Stop Mode; Typical Spi Interface - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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• Serial data output (also referred to as slave in/master out, or SIMO)
• Shift-clock (also referred to as SPICLK)
• Slave-enable signal (also referred to as SPISTE)
A typical SPI interface with a single slave device is shown in
The master device controls the flow of communication by providing shift-clock and slave-enable signals.
The slave-enable signal is an optional active-low signal that enables the serial data input and output of the
slave device (device not sending out the clock).
In the absence of a dedicated slave-enable signal, communication between the master and slave is
determined by the presence or absence of an active shift-clock. When the McBSP is operating in SPI
master mode and the SPISTE signal is not used by the slave SPI port, the slave device must remain
enabled at all times, and multiple slaves cannot be used.

15.7.2 Clock Stop Mode

The clock stop mode of the McBSP provides compatibility with the SPI protocol. When the McBSP is
configured in clock stop mode, the transmitter and receiver are internally synchronized so that the McBSP
functions as an SPI master or slave device. The transmit clock signal (CLKX) corresponds to the serial
clock signal (SPICLK) of the SPI protocol, while the transmit frame-synchronization signal (FSX) is used
as the slave-enable signal (SPISTE).
The receive clock signal (MCLKR) and receive frame-synchronization signal (FSR) are not used in the
clock stop mode because these signals are internally connected to their transmit counterparts, CLKX and
FSX.

15.7.3 Bits Used to Enable and Configure the Clock Stop Mode

The bits required to configure the McBSP as an SPI device are introduced in
shows how the various combinations of the CLKSTP bit and the polarity bits CLKXP and CLKRP create
four possible clock stop mode configurations. The timing diagrams in
CLKSTP, CLKXP, and CLKRP.
Table 15-14. Bits Used to Enable and Configure the Clock Stop Mode
Bit Field
CLKSTP bits of SPCR1
CLKXP bit of PCR
CLKRP bit of PCR
CLKXM bit of PCR
SPRUHE8E – October 2012 – Revised November 2019
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Figure 15-36. Typical SPI Interface
SPI-compliant
master
SPICLK
SPISIMO
SPISOMI
SPISTE SPISTE
Description
Use these bits to enable the clock stop mode and to select one of two timing variations.
(See also Table 15-15.)
This bit determines the polarity of the CLKX signal. (See also
This bit determines the polarity of the MCLKR signal. (See also
This bit determines whether CLKX is an input signal (McBSP as slave) or an output
signal (McBSP as master).
Copyright © 2012–2019, Texas Instruments Incorporated
SPI Operation Using the Clock Stop Mode
Figure 15-36.
SPI-compliant
slave
SPICLK
SPISIMO
SPISOMI
Table
Section 15.7.4
C28 Multichannel Buffered Serial Port (McBSP)
15-14. Table 15-15
show the effects of
Table 15-15.)
Table 15-15.)
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