Interrupt 128-133 Clear Enable (Dis4) Register; Interrupt 0-31 Set Pending (Pend0) Register; Interrupt 128-133 Clear Enable (Dis4) Register Field Descriptions; Interrupt 0-31 Set Pending (Pend0) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

NVIC Register Descriptions
25.5.10 Interrupt 128-133 Clear Enable (DIS4) Register, offset 0x190
The Interrupt 128-133 Clear Enable (DIS2) register disables interrupts. Bit 0 corresponds to Interrupt 128;
bit 5 corresponds to Interrupt 133. See the Cortex-M3 Processor chapter for interrupt assignments.
Note: This register can only be accessed from privileged mode.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-20. Interrupt 128-133 Clear Enable (DIS4) Register Field Descriptions
Bit Field
31-6 Reserved
5-0 INT
25.5.11 Interrupt 0-31 Set Pending (PEND0) Register, offset 0x200
The Interrupt 0-31 Set Pending (PEND0) register forces interrupts into the pending state and shows which
interrupts are pending. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See the Cortex-
M3 Processor chapter for interrupt assignments.
Note: This register can only be accessed from privileged mode.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-21. Interrupt 0-31 Set Pending (PEND0) Register Field Descriptions
Bit Field
31-0 INT
1654
Cortex-M3 Peripherals
Figure 25-14. Interrupt 128-133 Clear Enable (DIS4) Register
Reserved
R-0
Value Description
Reserved
Interrupt Disable
0 On a read, indicates the interrupt is disabled. On a write, no effect.
1 On a read, indicates the interrupt is enabled. On a write, clears the corresponding INT[n] bit in the
EN2 register, disabling interrupt [n].
Figure 25-15. Interrupt 0-31 Set Pending (PEND0) Register
Value Description
Interrupt Set Pending
0 On a read, indicates that the interrupt is not pending. On a write, no effect.
1 On a read, indicates that the interrupt is pending. On a write, the corresponding interrupt is set to
pending even if it is disabled..
If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be
cleared by setting the corresponding INT[n] bit in the UNPEND0 register.
Copyright © 2012–2019, Texas Instruments Incorporated
INT
R/W-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
6 5 0
INT
R/W-0
0
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