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Getting Started With TMS570LS Microcontrollers
Sunil Oak
This application report provides a brief overview of the TMS570LS series of microcontrollers. It
describes the initialization procedure for the TMS570LS series of microcontrollers. The
document also shows code fragments from source files that are generated using the HALCoGen
tool. All code constructs used in this document are also defined in header files also generated by
the same utility.
1
Block Diagram ................................................................................................................................. 3
2
Overview of Features ...................................................................................................................... 4
3
Standard Initialization Sequence for TMS570LS Microcontrollers ............................................. 7
3.1 Enabling Floating Point Coprocessor (FPU) ............................................................................. 8
3.2 Initialization of Cortex-R4F Registers ........................................................................................ 9
3.3 Initialize stack pointers for all CPU operating modes .............................................................. 11
3.4 Enable the Cortex-R4F CPU"s Vectored Interrupt Controller (VIC) Port ................................. 12
3.5 Configure Flash Access .......................................................................................................... 13
3.6 Configure flash bank and pump power modes ........................................................................ 14
3.7 Configure PLLs ........................................................................................................................ 17
3.7.1 FMzPLL ....................................................................................................................... 17
3.7.2 FPLL ............................................................................................................................ 20
3.8 Enable Clock Sources ............................................................................................................. 22
3.8.1 Available Clock Sources on TMS570LS Microcontrollers ........................................... 22
3.8.2 Control Registers for Enabling and Disabling Clock Sources ...................................... 23
3.8.3 Example Clock Source Configuration .......................................................................... 24
3.9 Clock Domains ........................................................................................................................ 25
3.9.1 Mapping Clock Domains to Clock Sources ................................................................. 26
3.9.2 Example Clock Domain Mapping ................................................................................ 27
3.9.3 Configuring VCLK and VCLK2 Frequencies ................................................................ 27
3.10 Run CPU Self-Test .................................................................................................................. 29
3.11 Release Reset and Clocks to Peripherals ............................................................................... 30
3.12 Memories" Self-Test ................................................................................................................ 31
3.13 Memories" Auto-Initialization ................................................................................................... 32
3.14 Vectored Interrupt Manager Configuration .............................................................................. 34
3.14.1 Example VIM RAM Configuration ................................................................................ 34
3.14.2 Configure Interrupts to be Fast Interrupts or Normal Interrupts ................................... 36
3.14.3 Enabling Interrupts ...................................................................................................... 36
3.15 Additional Initializations Required by Compiler ....................................................................... 39
3.16 Call the Main Application ......................................................................................................... 39
ABSTRACT
Contents
Application Report
Lit. Number - Month Year
AEC-Automotive Microcontrollers
1
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Related Manuals for Texas Instruments TMS570LS
Summary of Contents for Texas Instruments TMS570LS
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Page 1: Table Of Contents
AEC-Automotive Microcontrollers ABSTRACT This application report provides a brief overview of the TMS570LS series of microcontrollers. It describes the initialization procedure for the TMS570LS series of microcontrollers. The document also shows code fragments from source files that are generated using the HALCoGen tool. - Page 2 Figure 27. Interrupt Enable Clear Register 0: REQENACLR0, Address = 0xFFFFFE40 ....37 Figure 28. Interrupt Enable Clear Register 1: REQENACLR1, Address = 0xFFFFFE44 ....38 Tables Table 1. Clock Sources on TMS570LS Microcontrollers ............. 22 Table 2. Clock Domains on TMS570LS Microcontrollers ............25 Getting Started With TMS570LS Microcontrollers...
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Page 3: Block Diagram
Overwrite this text with the Lit. Number Block Diagram Figure 1 shows a high-level block diagram of the TMS570LS series microcontroller. Figure 1. Device Block Diagram ETMDATA[31:0] TRST ETMTRACECTL CCM-R4 ETMTRACECLKOUT w ith RTCK ICEPick ETMTRACECLKIN LIN1RX 160kB LIN1 Cortex-R4F... -
Page 4: Overview Of Features
Overwrite this text with the Lit. Number Overview of Features The TMS570LS series is a high-performance microcontroller family which has been certified for use in IEC 61508 SIL3 safety systems. The microcontrollers included in the TMS570LS Series are: – TMS570LS20216 –... - Page 5 8 KB message RAM with parity protection Dedicated transfer unit (FTU) Parity protection for transfer unit configuration memory Dedicated MPU to protect against erroneous transfers by FTU – Three Multi-Buffered Serial Peripheral Interface (MibSPI) Controllers Getting Started With TMS570LS Microcontrollers...
- Page 6 Allows application to update parameters without re-programming the flash – Data Modification Module (DMM) Provides ability to modify data anywhere within the 4GB addressable space – RAM Trace Port (RTP) Provides a high-speed trace of RAM accesses Getting Started With TMS570LS Microcontrollers...
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Page 7: Standard Initialization Sequence For Tms570Ls Microcontrollers
A typical basic sequence to be followed for initialization and configuration of key features on the TMS570LS Series microcontrollers is summarized below and detailed in the following sections. This is not a mandatory sequence. Applications that are non-safety-critical can choose to not use the ECC feature for flash and RAM accesses, for example. -
Page 8: Enabling Floating Point Coprocessor (Fpu)
MRC p15, #0x0, r0, c1, c0, #2 MOV r3, #0xf00000 ORR r0, r0, r3 MCR p15, #0x0, r0, c1, c0, #2 MRC p15, #0x0, r0, c0, c0 Enable the FPU MOV r0, #0x40000000 FMXR FPEXC, r0 Getting Started With TMS570LS Microcontrollers... -
Page 9: Initialization Of Cortex-R4F Registers
Overwrite this text with the Lit. Number Initialization of Cortex-R4F Registers The TMS570LS series of microcontrollers include dual Cortex-R4F CPUs running in a lock-step operation mode. A Core Compare Module (CCM-R4) compares the output signals from each R4F CPU. Any difference in the two CPUs‟ outputs is flagged as a fault of a high severity level. - Page 10 Initialize CPU return stack Getting Started With TMS570LS Microcontrollers...
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Page 11: Initialize Stack Pointers For All Cpu Operating Modes
The Cortex-R4F CPU can operate in one of several modes: User mode (USR) is the usual mode for the execution of ARM or Thumb programs. It is used for executing most application programs. Many control registers on the TMS570LS microcontroller are not writable in user mode. -
Page 12: Enable The Cortex-R4F Cpu"S Vectored Interrupt Controller (Vic) Port
The VIC port is disabled upon any CPU reset and must be enabled by the application. The VIC is enabled by setting the VE bit in the CPU‟s System Control Register, as shown below. p15, #0, r0, c1, c0, #0x01000000 p15, #0, r0, c1, c0, Getting Started With TMS570LS Microcontrollers... -
Page 13: Configure Flash Access
The flash memory on the TMS570LS series microcontrollers is a non-volatile electrically erasable and programmable memory. The TMS570LS microcontrollers contain a digital wrapper module that manages all accesses to the flash memory. A flash access can be completed without any wait states required for bus master clock speeds up to 36MHz. -
Page 14: Configure Flash Bank And Pump Power Modes
Overwrite this text with the Lit. Number Configure flash bank and pump power modes The flash banks and pump used on the TMS570LS series microcontrollers support three different operating modes to optimize power consumption. a. Active mode Flash bank sense amplifiers and sense reference are enabled All circuits of flash charge pump are enabled b. -
Page 15: Figure 4. Flash Bank Access Control Register: Fbac, Address = 0Xfff8703C
(VREAD) and the time when the flash bank starts its own power up sequence. NOTE: The flash banks have hard-coded timings for transitioning from sleep to standby to active power states. These timings are not configurable by the application. Getting Started With TMS570LS Microcontrollers... -
Page 16: Figure 5. Flash Pump Access Control Register 1: Fpac1, Address = 0Xfff87048
The PSLEEP field configures the time that the flash pump takes for transitioning from the sleep state to the standby state. This is specified in terms of HCLK/2 cycles. Please check the TMS570LS datasheet to identify the minimum time required for the flash pump to switch from the sleep state to the standby state. -
Page 17: Configure Plls
This mode is disabled by default, and the application can enable it in applications sensitive to noise emissions. The TMS570LS microcontrollers also contain a second non-modulating PLL macro. This is the FPLL macro. The FPLL can be independently configured to generate a second high-frequency clock source for specific uses. -
Page 18: Figure 8. Pll Control Register 1: Pllctl1, Address = 0Xffffff70
CLKIN frequency itself is supplied as the output from the FMzPLL macro. 3.7.1.3 FMzPLL Configuration The FMzPLL has two registers (PLLCTL1 and PLLCTL2) located within the System module on the TMS570LS microcontrollers. These are described now. Figure 8. PLL Control Register 1: PLLCTL1, Address = 0xFFFFFF70 Reset-On-Slip (ROS) selects whether a PLL slip condition causes a system reset or not. -
Page 19: Figure 9. Pll Control Register 2: Pllctl2, Address = 0Xffffff74
NOTE: NB must be set to 7 when modulation is not used. This is also the default value. ODPLL defines the OD-divider. – OD = ODPLL + 1 – / OD post-ODCLK VCOCLK SPR_AMOUNT defines the frequency modulation depth divider. – NV = SPR_AMOUNT + 1 Getting Started With TMS570LS Microcontrollers... -
Page 20: Fpll
1 to 15. The output clock is subsequently divided by an R-divider, which ranges from 1 to 8. The output of the R-divider is available for use as a clock source for any device clock domain. Getting Started With TMS570LS Microcontrollers... -
Page 21: Figure 11. Pll Control Register 3: Pllctl3, Address = 0Xffffe100
Overwrite this text with the Lit. Number 3.7.2.2 FPLL Configuration The FPLL is configured using the PLL control register 3 in the system module of the TMS570LS microcontroller. Figure 11. PLL Control Register 3: PLLCTL3, Address = 0xFFFFE100 OSC_DIV defines the NR-divider of the FPLL. -
Page 22: Enable Clock Sources
Overwrite this text with the Lit. Number Enable Clock Sources 3.8.1 Available Clock Sources on TMS570LS Microcontrollers The TMS570LS microcontrollers support 5 different clock sources, as listed in the table below. Table 1. Clock Sources on TMS570LS Microcontrollers Clock Source... -
Page 23: Control Registers For Enabling And Disabling Clock Sources
Each bit of the CSDIS controls the clock source of the same number: bit 0 controls clock source 0, bit 1 controls clock source 1, and so on. Figure 12 also shows the default states of the clock sources supported on the TMS570LS microcontrollers: –... -
Page 24: Example Clock Source Configuration
The above configuration enables clock sources 0, 1, 4, 5, and 6. The clock sources 2, 3 and 7 are not implemented on the TMS570LS microcontrollers and must be left disabled. Of the clock sources that are enabled, number 0, 4 and 5 are enabled by default and will have become valid by the time the processor is released from reset upon a power-up. -
Page 25: Clock Domains
Overwrite this text with the Lit. Number Clock Domains There are multiple clock domains on the TMS570LS microcontrollers to ease the configuration and controllability of the different modules using these clock domains. Table 2. Clock Domains on TMS570LS Microcontrollers Domain Name... -
Page 26: Mapping Clock Domains To Clock Sources
Overwrite this text with the Lit. Number 3.9.1 Mapping Clock Domains to Clock Sources The system module on the TMS570LS microcontrollers contains registers that allow the clock domains to be mapped to any of the available clock sources. These registers are defined now. -
Page 27: Example Clock Domain Mapping
3.9.3 Configuring VCLK and VCLK2 Frequencies The VCLK and VCLK2 clock signals are divided down from the HCLK clock signal. These are independent dividers that can be configured via the system module Clock Control Register (CLKCNTL), as shown below. Getting Started With TMS570LS Microcontrollers... -
Page 28: Figure 18. Peripheral Clock Control Register: Clkcntl, Address = 0Xffffffd0
NOTE: There must be some delay between configuring the divide ratios for VCLK2 and VCLK. systemREG1->CLKCNTL |= 0x00000000U ; // VCLK2 = HCLK/1 temp = systemREG1->CLKCNTL; // dummy read to cause delay systemREG1->CLKCNTL |= 0x00010000U; // VCLK = HCLK/2 Getting Started With TMS570LS Microcontrollers... -
Page 29: Run Cpu Self-Test
Overwrite this text with the Lit. Number 3.10 Run CPU Self-Test Please refer to chapter 7 of the Technical Reference Manual for the TMS570LS Microcontroller for information on the configuration and execution of the CPU self-test. Getting Started With TMS570LS Microcontrollers... -
Page 30: Release Reset And Clocks To Peripherals
PCR module registers for clearing the power down states of peripheral modules (PSPWRDWNCLRx). Please refer to the datasheet for the TMS570LS Microcontrollers for information on the peripheral select quadrants for each peripheral. -
Page 31: Memories" Self-Test
Overwrite this text with the Lit. Number 3.12 Memories’ Self-Test Please refer to the Technical Reference Manual for the TMS570LS microcontrollers for information on executing the self-test on the on-chip memories using the programmable BIST (PBIST) engine. Getting Started With TMS570LS Microcontrollers... -
Page 32: Memories" Auto-Initialization
Overwrite this text with the Lit. Number 3.13 Memories’ Auto-Initialization The system module on the TMS570LS microcontroller allows all on-chip SRAMs to be initialized in hardware. This is especially essential since all the on-chip memories support some form of read protection. The CPU data RAM supports ECC while the peripheral memories support parity error detection. -
Page 33: Figure 21. Memory Self-Test / Initialization Status Register: Mstcgstat, Address
The application can poll this bit. systemREG1->MINITGCR = 0xA; // Enable memory init systemREG1->MSIENA = 0xFFFFFFFF; // Select all SRAMs for init while (!(systemREG1->MSTCGSTAT & 0x00000100U)); // Wait until memory init is done Getting Started With TMS570LS Microcontrollers... -
Page 34: Vectored Interrupt Manager Configuration
The VIM module contains a memory that holds the starting addresses of the interrupt service routines for each interrupt enabled in the application. This memory starts at base address 0xFFF82000 on the TMS570LS microcontrollers. It is organized in 65 words of 32 bits. Figure 22. VIM Interrupt Address Memory Map 3.14.1 Example VIM RAM Configuration... - Page 35 Getting Started With TMS570LS Microcontrollers...
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Page 36: Configure Interrupts To Be Fast Interrupts Or Normal Interrupts
FIQ interrupt. As shown, the interrupt requests 0 and 1 are always FIQ. All others are IRQ interrupts by default. 3.14.3 Enabling Interrupts Control registers in the VIM module allow each interrupt request to be enabled or disabled. Getting Started With TMS570LS Microcontrollers... -
Page 37: Figure 25. Interrupt Enable Set Register 0: Reqenaset0, Address = 0Xfffffe30
IRQ or an FIR exception to the Cortex-R4F CPU. The interrupt requests 0 and 1 are always enabled and cannot be disabled. Figure 27. Interrupt Enable Clear Register 0: REQENACLR0, Address = 0xFFFFFE40 Getting Started With TMS570LS Microcontrollers... -
Page 38: Figure 28. Interrupt Enable Clear Register 1: Reqenaclr1, Address = 0Xfffffe44
Setting any bit in the interrupt enable clear registers disables the corresponding interrupt. When an interrupt is disabled, it does not prevent the interrupt flag to get set when the interrupt condition is generated but no IRQ or FIR exception is generated for the Cortex-R4F CPU. Getting Started With TMS570LS Microcontrollers... -
Page 39: Additional Initializations Required By Compiler
3.16 Call the Main Application This is a normal function call when using C/C++. It could be a branch or branch-link to the name of the routine that executes the application. For example: main(); exit(); Getting Started With TMS570LS Microcontrollers...
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