Table of Contents
Advertisement
NVIC Register Descriptions
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-24. Interrupt 96-127 Set Pending (PEND3) Register Field Descriptions
Bit
Field
31-0
INT
25.5.15 Interrupt 128-133 Set Pending (PEND4) Register, offset 0x210
The Interrupt 128-133 Set Pending (PEND4) register forces interrupts into the pending state and shows
which interrupts are pending. Bit 0 corresponds to Interrupt 128; bit 5 corresponds to Interrupt 133. See
the Cortex-M3 Processor chapter for interrupt assignments.
Note: This register can only be accessed from privileged mode.
31
28 27
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-25. Interrupt 128-133 Set Pending (PEND4) Register Field Descriptions
Bit
Field
31-6
Reserved
5-0
INT
1656
Cortex-M3 Peripherals
Figure 25-18. Interrupt 96-127 Set Pending (PEND3) Register
Value
Description
Interrupt Set Pending
0
On a read, indicates that the interrupt is not pending. On a write, no effect.
1
On a read, indicates that the interrupt is pending. On a write, the corresponding interrupt is set to
pending even if it is disabled.
If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be
cleared by setting the corresponding INT[n] bit in the UNPEND3 register.
Figure 25-19. Interrupt 128-133 Set Pending (PEND4) Register
Reserved
R-0
Value
Description
Reserved
Interrupt Set Pending
0
On a read, indicates that the interrupt is not pending. On a write, no effect.
1
On a read, indicates that the interrupt is pending. On a write, the corresponding interrupt is set to
pending even if it is disabled.
If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be
cleared by setting the corresponding INT[n] bit in the UNPEND2 register.
Copyright © 2012–2019, Texas Instruments Incorporated
INT
R/W-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
0
6
5
0
INT
R/W-0
Submit Documentation Feedback
Advertisement
Chapters
Table of Contents
