Sleep Mode Clock Gating Control Register 1 (Scgc1); Sleep Mode Clock Gating Control Register 1 (Scgc1) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 1-122. Run Mode Clock Gating Control Register 1 (RCGC1) Field Descriptions (continued)
Bit Field
6 SSI2
5 SSI1
4 SSI0
3 UART3
2 UART2
1 UART1
0 UART0

1.13.7.17 Sleep Mode Clock Gating Control Register 1 (SCGC1)

Figure 1-112. Sleep Mode Clock Gating Control Register 1 (SCGC1)
31
23
Reserved
15 14
Reserved I2C1
R-0 R/W-0
7 6
SSI3 SSI2
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-123. Sleep Mode Clock Gating Control Register 1 (SCGC1) Field Descriptions
Bit Field
31 Reserved
30 EPI
29-20 Reserved
SPRUHE8E – October 2012 – Revised November 2019
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Value Description
SSI2 Clock Gating Control in Run Mode
This bit controls the clock gating for the SSI2 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
SSI1 Clock Gating Control in Run Mode
This bit controls the clock gating for the SSI1 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
SSI0 Clock Gating Control in Run Mode
This bit controls the clock gating for the SSI0 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
UART3 Clock Gating Control in Run Mode
This bit controls the clock gating for the UART3 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
UART2 Clock Gating Control in Run Mode
This bit controls the clock gating for the UART2 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
UART1 Clock Gating Control in Run Mode
This bit controls the clock gating for the UART1 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
UART0 Clock Gating Control in Run Mode
This bit controls the clock gating for the UART0 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
20
R-0
13 12
Reserved I2C0
R-0 R/W-0
5 4
SSI1 SSI0
R/W-0 R/W-0
Value Description
Reserved
EPI Clock Gating Control in Sleep Mode
This bit controls the clock gating for the EPI module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
19 18
TIMER3 TIMER2
R/W-0 R/W-0
11
3 2
UART3 UART2
R/W-0 R/W-0
System Control Registers
24
17 16
TIMER1 TIMER0
R/W-0 R/W-0
8
Reserved
R-0
1 0
UART1 UART0
R/W-0 R/W-0
System Control and Interrupts
235