Gpio Trip Input Select Registers - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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(1)
Name
GPGPUD
AIOMUX1
AIOMUX2
AIODIR
(1)
Name
GPTRIP1SEL
GPTRIP2SEL
GPTRIP3SEL
GPTRIP4SEL
GPTRIP5SEL
GPTRIP6SEL
GPTRIP7SEL
GPTRIP8SEL
GPIOLPMSEL1
GPIOLPMSEL2
GPTRIP9SEL
GPTRIP10SEL
GPTRIP11SEL
GPTRIP12SEL
(1)
In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by the
master or an Address Negative Acknowledge executed by the slave.
To plan configuration of the GPIO module, consider the following steps:
1. Plan the device pin-out:
Through a pin multiplexing scheme, a lot of flexibility is provided for assigning functionality to the
GPIO-capable pins. Before getting started, look at the peripheral options available for each pin, and
plan pin-out for your specific system. Will the pin be used as a general purpose input or output (GPIO)
or as one of up to three available peripheral functions? Knowing this information will help determine
how to further configure the pin.
2. Select if the GPIO will be C28 core controlled:
If the pin will be used as a C28 GPIO or peripheral, the correct bits must be set in the GPIOCSEL
register. This register is located in the M3 GPIO register space.
3. Enable or disable internal pull-up resistors:
To enable or disable the internal pullup resistors, write to the respective bits in the GPIO pullup disable
(GPIOPUR) register. This register is located in the M3 GPIO register space. All GPIO-capable pins
have the pullup disabled by default. The AIOx pins do not have internal pull-up resistors.
4. Select input qualification:
SPRUHE8E – October 2012 – Revised November 2019
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Table 4-36. GPIO Control Registers (continued)
Address Size (x16)
0x6F8C 2
0x6FB6 2
0x6FB8 2
0x6FBA 2
Table 4-37. GPIO Trip Input Select Registers
Address Size (x16)
0x5FE0 1
0x5FE1 1
0x5FE2 1
0x5FE3 1
0x5FE4 1
0x5FE5 1
0x5FE6 1
0x5FE7 1
0x5FE8 2
0x5FEA 2
0x5FF0 1
0x5FF1 1
0x5FF2 1
0x5FF3 1
Copyright © 2012–2019, Texas Instruments Incorporated
C28 General-Purpose Input/Output (GPIO)
Register Description
GPIO G Pull Up Disable Register (GPIO192 -
GPIO199)
Analog IO MUX 1 Register (AIO0 to AIO15)
Analog IO MUX 2 Register (AIO16 to AIO31)
Analog IO Direction Register (AIO0 AIO31)
Description
GPTRIP1 (TZ1n) Input Select Register (GPIO0 -
GPIO63)
GPTRIP2 (TZ2n, ADCEXTTRIG) Input Select
Register (GPIO0 - GPIO63)
GPTRIP3 (TZ3n) Input Select Register (GPIO0 -
GPIO63)
GPTRIP4 (XINT1) Input Select Register (GPIO0 -
GPIO63)
GPTRIP5 (XINT2) Input Select Register (GPIO0 -
GPIO63)
GPTRIP6 (XINT3) Input Select Register (GPIO0 -
GPIO63)
GPTRIP7 (ECAP1) Input Select Register (GPIO0 -
GPIO63)
GPTRIP8 (ECAP2) Input Select Register (GPIO0 -
GPIO63)
LPM GPIO Select 1 Register (GPIO0 - GPIO31)
LPM GPIO Select 2 Register (GPIO32 - GPIO63)
GPTRIP9 (ECAP3) Input Select Register (GPIO0 -
GPIO63)
GPTRIP10 (ECAP4) Input Select Register (GPIO0
- GPIO63)
GPTRIP11 (ECAP5) Input Select Register (GPIO0
- GPIO63)
GPTRIP12 (ECAP6) Input Select Register (GPIO0
- GPIO63)
General-Purpose Input/Output (GPIO)
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