Set The Receive Interrupt Mode; Set The Receive Frame-Synchronization Mode; Register Bits Used To Set The Receive Interrupt Mode; Register Bits Used To Set The Receive Frame Synchronization Mode - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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15.8.14 Set the Receive Interrupt Mode

The RINTM bits (see
CPU.
The receive interrupt (RINT) informs the CPU of changes to the serial port status. Four options exist for
configuring this interrupt. The options are set by the receive interrupt mode bits, RINTM, in SPCR1.
Table 15-35. Register Bits Used to Set the Receive Interrupt Mode
Register Bit Name
SPCR1 5-4 RINTM

15.8.15 Set the Receive Frame-Synchronization Mode

The bits described in
of the FSR pin.
15.8.15.1 Receive Frame-Synchronization Modes
Table 15-37 shows how you can select various sources to provide the receive frame-synchronization
signal and the effect on the FSR pin. The polarity of the signal on the FSR pin is determined by the FSRP
bit.
In digital loopback mode (DLB = 1), the transmit frame-synchronization signal is used as the receive
frame-synchronization signal.
Also in the clock stop mode, the internal receive clock signal (MCLKR) and the internal receive frame-
synchronization signal (FSR) are internally connected to their transmit counterparts, CLKX and FSX.
Table 15-36. Register Bits Used to Set the Receive Frame Synchronization Mode
Register Bit
PCR 10
SPRUHE8E – October 2012 – Revised November 2019
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Table 15-35) determine which event generates a receive interrupt request to the
Function
Receive interrupt mode
RINTM = 00 RINT generated when RRDY changes from 0 to 1. Interrupt on
every serial word by tracking the RRDY bit in SPCR1.
Regardless of the value of RINTM, RRDY can be read to
detect the RRDY = 1 condition.
RINTM = 01 RINT generated by an end-of-block or end-of-frame condition
in the receive multichannel selection mode. In the multichannel
selection mode, interrupt after every 16-channel block
boundary has been crossed within a frame and at the end of
the frame. For details, see
Between Block Transfers. In any other serial transfer case, this
setting is not applicable and, therefore, no interrupts are
generated.
RINTM = 10 RINT generated by a new receive frame-synchronization pulse.
Interrupt on detection of receive frame-synchronization pulses.
This generates an interrupt even when the receiver is in its
reset state. This is done by synchronizing the incoming frame-
synchronization pulse to the CPU clock and sending it to the
CPU via RINT.
RINTM = 11 RINT generated when RSYNCERR is set. Interrupt on frame-
synchronization error. Regardless of the value of RINTM,
RSYNCERR can be read to detect this condition. For
information on using RSYNCERR, see
Unexpected Receive Frame-Synchronization Pulse.
Table 15-36 determine the source for receive frame synchronization and the function
Name Function
FSRM Receive frame-synchronization mode
FSRM = 0
FSRM = 1
Copyright © 2012–2019, Texas Instruments Incorporated
Section 15.6.7.3, Using Interrupts
Section
Receive frame synchronization is supplied by an
external source via the FSR pin.
Receive frame synchronization is supplied by
the sample rate generator. FSR is an output pin
reflecting internal FSR, except when GSYNC = 1
in SRGR2.
C28 Multichannel Buffered Serial Port (McBSP)
Receiver Configuration
Reset
Type Value
R/W 00
15.5.3,
Reset
Type Value
R/W 0
1125