Interrupt Register (Can Int) [Offset = 0X10]; Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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CAN Control Registers

Table 23-8. Bit Timing Register Field Descriptions (continued)

NOTE: This register is only writable if CCE and Init bits in the CAN Control Register are set.

NOTE: The CAN bit time may be programmed in the range of 8 to 25 time quanta.

NOTE: The CAN time quantum may be programmed in the range of 1 to1024 CAN_CLK periods.

With a CAN_CLK of 8 MHz and BRPE = 0x00, the reset value of 0x00002301 configures the CAN for a bit

rate of 500kBit/s.

For details see

23.15.5 Interrupt Register (CAN INT)

The Interrupt register (CAN INT) is shown and described in the figure and table below.

LEGEND: R = Read; -n = value after reset

M3 Controller Area Network (CAN)

Baud Rate Prescaler Value by which the CAN_CLK frequency is divided for generating the bit time

quanta. The bit time is built up from a multiple of this quanta. Valid programmed values are 0 to 63.

The actual BRP value interpreted for the Bit Timing will be the programmed BRP value + 1.

Figure 23-23. Interrupt Register (CAN INT) [offset = 0x10]

Table 23-9. Descriptions

Interrupt 1 Identifier (indicates the message object with the highest pending interrupt)

No interrupt is pending

Number of the mailbox which caused the interrupt.

If several interrupts are pending, the CAN Interrupt register will point to the pending interrupt

with the highest priority.

The CAN1INT interrupt line remains active until INT1ID reaches value 0 (the cause of the

interrupt is reset) or until IE1 is cleared.

A message interrupt is cleared by clearing the mailbox's IntPnd bit.

Among the message interrupts, the mailbox's interrupt priority decreases with increasing

message number.

Int0ID[15:0]

SPRUHE8E – October 2012 – Revised November 2019

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