I2C Extended Mode Register (I2Cemdr); Pin Diagram Showing The Effects Of The Digital Loopback Mode (Dlb) Bit; I2C Extended Mode Register (I2Cemdr) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

I2C Module Registers
Figure 14-15. Pin Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit
2
To internal I C logic
2
From internal I C logic
I2
To internal C logic
To CPU
From CPU
From CPU
From CPU

14.5.2 I2C Extended Mode Register (I2CEMDR)

The I2C extended mode register is shown in
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-8. I2C Extended Mode Register (I2CEMDR) Field Descriptions
Bit Field
15-1 Reserved
0 BCM
1060
C28 Inter-Integrated Circuit Module
2
I C module
SCL_IN
SCL_OUT
I2CDRR
I2CSAR
I2COAR
I2CDXR
Figure 14-16. I2C Extended Mode Register (I2CEMDR)
Reserved
R-0
Value Description
Any writes to these bit(s) must always have a value of 0.
Backwards compatibility mode. This bit affects the timing of the transmit status bits (XRDY and
XSMT) in the I2CSTR register when in slave transmitter mode. See
Copyright © 2012–2019, Texas Instruments Incorporated
I2CRSR
DLB
0
1 I2CXSR
Address/data
Figure 14-16 and described in
SPRUHE8E – October 2012 – Revised November 2019
DLB
0 SCL
1 0
DLB
0 SDA
1 0
Table 14-8.
1
Figure 14-17 for details
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0
BCM
R/W-1