M3Nmi Flag Clear (Mnmiflgclr) Register; M3Nmi Flag Clear (Mnmiflgclr) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

System Control Registers
Table 1-73. M3NMI Flag (MNMIFLG) Register Field Descriptions (continued)
Bit Field
0 NMIINT

1.13.5.3 M3NMI Flag Clear (MNMIFLGCLR) Register

NOTE: If hardware is trying to set a bit to "1" while software is trying to clear a bit to "0" on the same
cycle, hardware has priority.
Users should clear the pending FAIL flag first and then clear the NMIINT flag.
31
15
7 6
C28PIENMIERR EXTGPIO
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-74. M3NMI Flag Clear (MNMIFLGCLR) Register Field Descriptions
Bit Field
31-10 Reserved
9 ACIBERR
8 C28NMIWDRST
7 C28PIENMIERR
6 EXTGPIO
5 C28BISTERR
204
System Control and Interrupts
Value Description
NMI Interrupt Flag
This bit indicates if an M3 NMI interrupt was generated. This bit can only be cleared by the user
writing to the respective bit in the NMIFLGCLR register or by an XRS reset.
No further NMI interrupts pulses are generated until this flag is cleared by the user.
0 No NMI interrupt generated
1 NMI interrupt generated
Figure 1-63. M3NMI Flag Clear (MNMIFLGCLR) Register
Reserved
R-0
5 4
C28BISTERR M3BISTERR
R/W-0 R/W-0
Value Description
Reserved
CIB Error NMI Flag Clear
0 Ignored; always reads back 0.
1 Clears the corresponding flag bit in the NMIFLG register.
C28 NMI WD Reset Flag Clear
0 Ignored; always reads back 0.
1 Clears the corresponding flag bit in the NMIFLG register.
C28 PIE NMIERR NMI Flag Clear
0 Ignored; always reads back 0.
1 Clears the corresponding flag bit in the NMIFLG register.
External GPIO NMI Flag Clear
0 Ignored; always reads back 0.
1 Clears the corresponding flag bit in the NMIFLG register.
C28 BIST Error Flag
0 Writes of 0 are ignored. Always reads back 0.
1 Writing a 1 to the respective bit clears the corresponding flag bit in the NMIFLG and NMISHDFLG
registers.
Note 1: If hardware is trying to set a bit to 1 while software is trying to clear a bit to 0 on the same
cycle, hardware has priority.
Note 2: Users should clear the pending FAIL flag first and then clear the NMIINT flag.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0:0
10
3 2
Reserved
R-0:0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
16
9 8
ACIBERR C28NMIWDRST
R/W-0 R/W-0
1 0
CLOCKFAIL NMIINT
R/W-0 R/W-0
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