Cx Shram Configuration Register 1 (Cxsrcr1); Cx Shram Configuration Register 1 (Cxsrcr1) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

RAM Control Module Registers
5.2.1.2

Cx SHRAM Configuration Register 1 (CxSRCR1)

31 30
23 22
15 14
7
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-14. Cx SHRAM Configuration Register 1 (CxSRCR1) Field Descriptions
Bit Field
31-27 Reserved
26 CPUWRPROTC5
25 DMAWRPROTC5
24 FETCHPROTC5
23-19 Reserved
18 CPUWRPROTC4
17 DMAWRPROTC4
16 FETCHPROTC4
15-11 Reserved
10 CPUWRPROTC3
9 DMAWRPROTC3
8 FETCHPROTC3
7-3 Reserved
2 CPUWRPROTC2
476
Internal Memory
Figure 5-5. Cx SHRAM Configuration Register 1 (CxSRCR1)
29 28
Reserved
R-0
21 20
Reserved
R-0
13 12
Reserved
R-0
Reserved
R-0
Value Description
Reserved
0 M3 CPU Write allowed to C5 RAM Block
1 M3 CPU Write not allowed to C5 RAM Block.
0 M3 uDMA Write allowed to C5 RAM Block.
1 M3 uDMA Write not allowed to C5 RAM Block.
0 M3 CPU Fetch allowed from C5 RAM Block.
1 M3 CPU Fetch not allowed from C5 RAM Block.
Reserved
0 M3 CPU Write allowed to C4 RAM Block.
1 M3 CPU Write not allowed to C4 RAM Block.
0 M3 uDMA Write allowed to C4 RAM Block.
1 M3 uDMA Write not allowed to C4 RAM Block.
0 M3 CPU Fetch allowed from C4 RAM Block.
1 M3 CPU Fetch not allowed from C4 RAM Block.
Reserved
0 M3 CPU Write allowed to C3 RAM Block.
1 M3 CPU Write not allowed to C3 RAM Block.
0 M3 uDMA Write allowed to C3 RAM Block.
1 M3 uDMA Write not allowed to C3 RAM Block.
0 M3 CPU Fetch allowed from C3 RAM Block.
1 M3 CPU Fetch not allowed from C3 RAM Block.
Reserved
0 M3 CPU Write allowed to C2 RAM Block.
1 M3 CPU Write not allowed to C2 RAM Block
Copyright © 2012–2019, Texas Instruments Incorporated
27 26
CPUWRPROT DMAWRPROT
C5
R/W-0
19 18
CPUWRPROT DMAWRPROT
C4
R/W-0
11 10
CPUWRPROT DMAWRPROT
C3
R/W-0
3 2
CPUWRPROT DMAWRPROT
C2
R/W-0
SPRUHE8E – October 2012 – Revised November 2019
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25 24
FETCHPROTC
C5 5
R/W-0 R/W-0
17 16
FETCHPROTC
C4 4
R/W-0 R/W-0
9 8
FETCHPROTC
C3 3
R/W-0 R/W-0
1 0
FETCHPROTC
C2 2
R/W-0 R/W-0