Mcbsp Exception/Error Conditions; Types Of Errors; Overrun In The Receiver - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Step 4. If necessary, enable the receiver and/or the transmitter.
If necessary, remove the receiver and/or transmitter from reset by setting RRST and/or XRST = 1.
Step 5. If necessary, enable the frame-synchronization logic of the sample rate generator.
After the required data acquisition setup is done (DXR[1,2] is loaded with data), set GRST = 1 in
SPCR2 if an internally generated frame-synchronization pulse is required. FSG is generated with an
active-high edge after the programmed number of CLKG clocks (FPER + 1) have elapsed.
Equation 4: CLKG Frequency
where the input clock is selected with the SCLKME bit of PCR and the CLKSM bit of SRGR2 in one of the
configurations shown in

15.5 McBSP Exception/Error Conditions

This section describes exception/error conditions and how to handle them.

15.5.1 Types of Errors

There are five serial port events that can constitute a system error:
• Receiver overrun (RFULL = 1)
This occurs when DRR1 has not been read since the last RBR-to-DRR copy. Consequently, the
receiver does not copy a new word from the RBR(s) to the DRR(s) and the RSR(s) are now full with
another new word shifted in from DR. Therefore, RFULL = 1 indicates an error condition wherein any
new data that can arrive at this time on DR replaces the contents of the RSR(s), and the previous word
is lost. The RSRs continue to be overwritten as long as new data arrives on DR and DRR1 is not read.
For more details about overrun in the receiver, see
• Unexpected receive frame-synchronization pulse (RSYNCERR = 1)
This occurs during reception when RFIG = 0 and an unexpected frame-synchronization pulse occurs.
An unexpected frame-synchronization pulse is one that begins the next frame transfer before all the
bits of the current frame have been received. Such a pulse causes data reception to abort and restart.
If new data has been copied into the RBR(s) from the RSR(s) since the last RBR-to-DRR copy, this
new data in the RBR(s) is lost. This is because no RBR-to-DRR copy occurs; the reception has been
restarted. For more details about receive frame-synchronization errors, see
• Transmitter data overwrite
This occurs when the CPU or DMA controller overwrites data in the DXR(s) before the data is copied
to the XSR(s). The overwritten data never reaches the DX pin. For more details about overwrite in the
transmitter, see
• Transmitter underflow (XEMPTY = 0)
If a new frame-synchronization signal arrives before new data is loaded into DXR1, the previous data
in the DXR(s) is sent again. This procedure continues for every new frame-synchronization pulse that
arrives until DXR1 is loaded with new data. For more details about underflow in the transmitter, see
Section 15.5.4.3.
• Unexpected transmit frame-synchronization pulse (XSYNCERR = 1)
This occurs during transmission when XFIG = 0 and an unexpected frame-synchronization pulse
occurs. An unexpected frame-synchronization pulse is one that begins the next frame transfer before
all the bits of the current frame have been transferred. Such a pulse causes the current data
transmission to abort and restart. If new data has been written to the DXR(s) since the last DXR-to-
XSR copy, the current value in the XSR(s) is lost. For more details about transmit frame-
synchronization errors, see

15.5.2 Overrun in the Receiver

RFULL = 1 in SPCR1 indicates that the receiver has experienced overrun and is in an error condition.
RFULL is set when all of the following conditions are met:
SPRUHE8E – October 2012 – Revised November 2019
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CLKG frequency +
Table 15-7.
Section 15.5.4.
Section 15.5.5.
Copyright © 2012–2019, Texas Instruments Incorporated
Input clock frequency
( CLKGDV ) 1 )
Section 15.5.2.
C28 Multichannel Buffered Serial Port (McBSP)
McBSP Exception/Error Conditions
Section 15.5.3.
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