Number Of Phases, Words, And Bits Per Frame; Single-Phase Frame Example; Dual-Phase Frame Example; Single-Phase Frame For A Mcbsp Data Transfer - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Frame Phases

15.3.1 Number of Phases, Words, and Bits Per Frame

Table 15-2 shows which bit-fields in the receive control registers (RCR1 and RCR2) and in the transmit
control registers (XCR1 and XCR2) determine the number of phases per frame, the number of words per
frame, and number of bits per word for each phase, for the receiver and transmitter. The maximum
number of words per frame is 128 for a single-phase frame and 256 for a dual-phase frame. The number
of bits per word can be 8, 12, 16, 20, 24, or 32 bits.
Table 15-2. Register Bits That Determine the Number of Phases, Words, and Bits
Operation
Reception
Reception
Transmission
Transmission

15.3.2 Single-Phase Frame Example

Figure 15-9 shows an example of a single-phase data frame containing one 8-bit word. Because the
transfer is configured for one data bit delay, the data on the DX and DR pins are available one clock cycle
after FS(R/X) goes active. The figure makes the following assumptions:
• (R/X)PHASE = 0: Single-phase frame
• (R/X)FRLEN1 = 0b: 1 word per frame
• (R/X)WDLEN1 = 000b: 8-bit word length
• (R/X)FRLEN2 and (R/X)WDLEN2 are ignored
• CLK(X/R)P = 0: Receive data clocked on falling edge; transmit data clocked on rising edge
• FS(R/X)P = 0: Active-high frame-synchronization signals
• (R/X)DATDLY = 01b: 1-bit data delay
Figure 15-9. Single-Phase Frame for a McBSP Data Transfer
CLK(R/X)
FS(R/X)
A1
D(R/X)

15.3.3 Dual-Phase Frame Example

Figure 15-10 shows an example of a frame where the first phase consists of two words of 12 bits each,
followed by a second phase of three words of 8 bits each. The entire bit stream in the frame is contiguous.
There are no gaps either between words or between phases.
Figure 15-10. Dual-Phase Frame for a McBSP Data Transfer
CLK(R/X)
FS(R/X)
D(R/X)
A XRDY gets asserted once per phase. So, if there are 2 phases, XRDY gets asserted twice (once per phase).
1082
C28 Multichannel Buffered Serial Port (McBSP)
Number of Phases Words per Frame Set With
1 (RPHASE = 0) RFRLEN1
2 (RPHASE = 1) RFRLEN1 and RFRLEN2
1 (XPHASE = 0) XFRLEN1
2 (XPHASE = 1) XFRLEN1 and XFRLEN2
A0 B7 B6 B5
Phase 1 Word 1
Phase 1 Word 2
Copyright © 2012–2019, Texas Instruments Incorporated
B4 B3 B2 B1 B0
Phase 2 Phase 2
Word 1 Word 2
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
Bits per Word Set With
RWDLEN1
RWDLEN1 for phase 1
RWDLEN2 for phase 2
XWDLEN1
XWDLEN1 for phase 1
XWDLEN2 for phase 2
C7 C6 C5
Phase 2
Word 3
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