Gptm Control (Gptmctl) Register, Offset 0X00C; Gptm Control (Gptmctl) Register; Gptm Control (Gptmctl) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Table of Contents

Table 2-7. GPTM Timer B Mode (GPTMTBMR) Register Field Descriptions (continued)

2.6.4 GPTM Control (GPTMCTL) Register, offset 0x00C

The GPTM Control (GPTMCTL) register is used alongside the GPTMCFG and GMTMTnMR registers to

fine-tune the timer configuration, and to enable other features such as timer stall and the output trigger.

Important: Bits in this register should only be changed when the TnEN bit for the respective timer is

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

SPRUHE8E – October 2012 – Revised November 2019

Submit Documentation Feedback

GPTM Timer B Mode. The timer mode is based on the timer configuration defined by bits 2:0 in the

GPTMCFG register.

One-shot timer mode

Periodic Ttimer mode

Capture mode

Figure 2-9. GPTM Control (GPTMCTL) Register

Table 2-8. GPTM Control (GPTMCTL) Register Field Descriptions

GPTM Timer B PWM Output Level

Output is unaffected.

Output is inverted.

GPTM Timer B Event Mode

Positive edge

Negative edge

GPTM Timer B Stall Enable

Timer B continues counting while the processor is halted by the debugger

Timer B freezes counting while the processor is halted by the debugger

If the processor is executing normally, the TBSTALL bit is ignored.

GPTM Timer B Enable

Timer B is disabled.

Timer B is enabled and begins counting or the capture logic is enabled based on the GPTMCFG

M3 General-Purpose Timers

Table of Contents