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Functional Description
The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a 16-bit
down-counter with a start value (and thus period) defined by the GPTMTnILR register. In this mode, the
PWM frequency and period are synchronous events and therefore guaranteed to be glitch free. PWM
mode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to 0x0, and
the TnMR field to 0x2.
When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down until it
reaches the 0x0 state. On the next counter cycle, the counter reloads its start value from the GPTMTnILR
register and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL register.
No interrupts or status bits are asserted in PWM mode.
The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its start
state), and is deasserted when the counter value equals the value in the GPTMTnMATCHR register.
Software has the capability of inverting the output PWM signal by setting the TnPWML bit in the
GPTMCTL register.
Figure 2-5
shows how to generate an output PWM with a 1-ms period and a 66% duty cycle assuming a
100-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML =1 configuration). For
this example, the start value is GPTMTnILR=0x186A0 and the match value is GPTMTnMATCHR=0x8235.
0x186A0
0x8235
TnPWML =0
Output
Signal
TnPWML =1
2.3.3 DMA Operation
The timers each have a dedicated µDMA channel and can provide a request signal to the µDMA
controller. The request is a burst type and occurs whenever a timer raw interrupt condition occurs. The
arbitration size of the µDMA transfer should be set to the amount of data that should be transferred
whenever a timer event occurs.
For example, to transfer 256 items, 8 items at a time every 10 ms, configure a timer to generate a periodic
timeout at 10 ms. Configure the µDMA transfer for a total of 256 items, with a burst size of 8 items. Each
time the timer times out, the µDMA controller transfers 8 items, until all 256 items have been transferred.
No other special steps are needed to enable Timers for µDMA operation. Refer to the Micro Direct
Memory Access (µDMA) chapter for more details about programming the µDMA controller.
312
M3 General-Purpose Timers
Figure 2-5. 16-Bit PWM Mode Example
Count
GPTMTnR=GPTMnMR
TnEN set
Copyright © 2012–2019, Texas Instruments Incorporated
GPTMTnR=GPTMnMR
SPRUHE8E – October 2012 – Revised November 2019
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