Ssicr0 Register; Ssicr0 Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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20.5.2.1 SSICR0 Register (Offset = 0h) [reset = 0h]
SSICR0 is shown in
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SSI Control 0
31 30 29 28
15 14 13 12
Bit Field
31-16 RESERVED
15-8 SCR
7 SPH
6 SPO
5-4 FRF
SPRUHE8E – October 2012 – Revised November 2019
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Figure 20-10 and described in
Table.
Figure 20-10. SSICR0 Register
27 26 25
11 10 9
SCR
R/W-0h
Table 20-4. SSICR0 Register Field Descriptions
Type Reset
R 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2012–2019, Texas Instruments Incorporated
Table 20-4.
24 23 22 21
RESERVED
R-0h
8 7 6 5
SPH SPO FRF
R/W- R/W- R/W-0h
0h 0h
Description
Reserved
SSI Serial Clock Rate
This bit field is used to generate the transmit and receive bit rate of
the SSI. The bit rate is: BR=SysClk/(CPSDVSR * (1 + SCR)) where
CPSDVSR is an even value from 2-254 programmed in the
SSICPSR register, and SCR is a value from 0-255.
Reset type: PER.RESET
SSI Serial clock PHase
This bit is only applicable to the Freescale SPI Format.The control
bit selects the clock edge that captures data and allows it to change
state. This bit has the most impact on the first bit transmitted by
either allowing or not allowing a clock transition before the first data
capture edge.
SPH
Value Description
0 Data is captured on the first clock edge transition.
1 Data is captured on the second clock edge transition.
Reset type: PER.RESET
SSI Serial clock POlarity
Value Description
0 A steady state Low value is placed on the pin SSInClk when data
is not being transferred.
1 A steady state High value is placed on the pin SSInClk when data
is not being transferred.
Reset type: PER.RESET
SSI FRame Format Select
Value Frame Format
0x0 Freescale SPI Frame Format
0x1 Synchronous Serial Frame Format Texas Instruments
0x2 Reserved
0x3 Reserved
Reset type: PER.RESET
M3 Synchronous Serial Interface (SSI)
SSI Registers
20 19 18 17
4 3 2 1
DSS
R/W-0h
16
0
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