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Register Descriptions
17.11.2 EPI Main Baud Rate (EPIBAUD) Register, offset 0x004
The system clock is used internally to the EPI controller. The baud rate counter can be used to divide the
system clock down to control the speed on the external interface. If the mode selected emits an external
EPI clock, this register defines the EPI clock emitted. If the mode selected does not use an EPI clock, this
register controls the speed of changes on the external interface. This register must be programmed
properly so that the speed of the external bus corresponds to the speed of the external peripheral and
puts acceptable current load on the pins. COUNT0 is the bit field used in all modes except in HB8 and
HB16 modes with dual chip selects and quad chip selects when different baud rates are selected. See
Section 17.11.8
and
address range specified by CS1. The EPIBAUD2 register configures the baud rates for CS2 and CS3.
The COUNTn field is not a straight divider or count. The EPI Clock on EPI0S31 is related to the COUNTn
field and the system clock as follows:
If COUNTn = 0,
EPIClockFreq = SystemClockFreq
otherwise
EPIClockFreq = SystemClockFreq / ([Countn / 2] + 1) × 2
where the symbol around COUNTn/2 is the floor operator; meaning the largest integer less than or equal
to COUNTn/2.
So, for example, a COUNTn of 0x0001 results in a clockrate of 1/2 (system clock); a COUNTn of 0x0002
or 0x0003 results in a clock rate of 1/4 (system clock).
The baud rate counter can also be configured as an integer divide by enabling INTDIV in the EPICFG
register. When enabled, COUNTn of 0x0000 or 0x0001 results in a clock rate equal to system clock.
COUNTn of 0x0002 results in a clock rate of 1/2 (system clock). COUNTn of 0x0003 results in a clock rate
of 1/3 (system clock).
Figure 17-29. EPI Main Baud Rate (EPIBAUD) Register [offset 0x004]
31
COUNT1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17-15. EPI Main Baud Rate (EPIBAUD) Register Field Descriptions
Bit
Field
31-16
COUNT1
15-0
COUNT0
1266
External Peripheral Interface (EPI)
Section
17.11.9. If different baud rates are used, COUNT0 is associated with the
R/W-0
Value
Description
Baud Rate Counter 1
This bit field is only valid with multiple chip selects which are enabled when the CSCFG field is 0x2
or 0x3 or the CSCFGEXT field is set to 1, with CSCFG field as 0x1 or 0x2 and the CSBAUD bit is
set in the EPIHBnCFG2 register.
0
A count of 0 means the system clock is used as is.
1
This bit field contains a counter used to divide the system clock by the count.
Baud Rate Counter 0
0
A count of 0 means the system clock is used as is.
1
This bit field contains a counter used to divide the system clock by the count.
Copyright © 2012–2019, Texas Instruments Incorporated
16 15
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
COUNT0
R/W-0
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