Digital Compare Capture Control Register (Dccapctl); Digital Compare Counter Capture Register (Dccap); Digital Compare Capture Control Register (Dccapctl) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 7-70. Digital Compare Filter Control Register (DCFCTL) Field Descriptions (continued)
Bit
Field
5-4
PULSESEL
3
BLANKINV
2
BLANKE
1-0
SRCSEL
Figure 7-121. Digital Compare Capture Control Register (DCCAPCTL)
15
7
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-71. Digital Compare Capture Control Register (DCCAPCTL) Field Descriptions
Bit
Field
15-2
Reserved
1
SHDWMODE
0
CAPE
Figure 7-122. Digital Compare Counter Capture Register (DCCAP)
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUHE8E – October 2012 – Revised November 2019
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Value
Description
Pulse Select For Blanking & Capture Alignment
00
Time-base counter equal to period (TBCTR = TBPRD)
01
Time-base counter equal to zero (TBCTR = 0x00)
10
Reserved
11
Reserved
Blanking Window Inversion
0
Blanking window not inverted
1
Blanking window inverted
Blanking Window Enable/Disable
0
Blanking window is disabled
1
Blanking window is enabled
Filter Block Signal Source Select
00
Source Is DCAEVT1 Signal
01
Source Is DCAEVT2 Signal
10
Source Is DCBEVT1 Signal
11
Source Is DCBEVT2 Signal
Reserved
R-0
Value
Description
Reserved
TBCTR Counter Capture Shadow Select Mode
0
Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR =
TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the
DCCAP register will return the shadow register contents.
1
Active Mode. In this mode the shadow register is disabled. CPU reads from the DCCAP register will
always return the active register contents.
TBCTR Counter Capture Enable/Disable
0
Disable the time-base counter capture.
1
Enable the time-base counter capture.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
2
DCCAP
R-0
C28 Enhanced Pulse Width Modulator (ePWM) Module
Registers
8
1
0
SHDWMODE
CAPE
R/W-0
R/W-0
0
807

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