Ethernet Mac Transmit Control (Mactctl) Register; Ethernet Mac Receive Control (Macrctl) Register Field Descriptions; Ethernet Mac Transmit Control (Mactctl) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Ethernet MAC Register Descriptions
Table 19-5. Ethernet MAC Receive Control (MACRCTL) Register Field Descriptions
Bit Field
31-5 Reserved
4 RSTFIFO
3 BADCRC
2 PRMS
1 AMUL
0 RXEN
19.6.4 Ethernet MAC Transmit Control (MACTCTL) Register, offset 0x00C
The Ethernet MAC Transmit Control (MACTCTL) register is shown and described in the figure and table
below.
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-6. Ethernet MAC Transmit Control (MACTCTL) Register Field Descriptions
Bit Field
31-5 Reserved
4 DUPLEX
3 Reserved
2 CRC
1428
M3 Ethernet Media Access Controller (EMAC)
Value Description
Reserved
Clear Receive FIFO
0 No effect.
1 Clear the receive FIFO. The receive FIFO should be cleared when software initialization is
performed.
This bit is automatically cleared when read. The receiver should be disabled (RXEN = 0), before a
reset is initiated (RSTFIFO = 1). This sequence flushes and resets the RX FIFO.
Enable Reject Bad CRC
0 Disables the rejection of frames with an incorrectly calculated CRC.
1 Enables the rejection of frames with an incorrectly calculated CRC. If a bad CRC is encountered,
the RXER bit in the MACRIS register is set and the receiver FIFO is reset.
Enable Promiscuous Mode
0 Disables Promiscuous mode, accepting only frames with the programmed Destination Address.
1 Enables Promiscuous mode, which accepts all valid frames, regardless of the specified Destination
Address.
Enable Multicast Frames
0 Disables the reception of multicast frames.
1 Enables the reception of multicast frames.
Enable Receiver
0 Disables the receiver. All frames are ignored.
1 Enables the Ethernet receiver
Figure 19-7. Ethernet MAC Transmit Control (MACTCTL) Register
R-0
Value Description
Reserved
Enable duplex mode
0 Disables duplex mode.
1 Enables duplex mode, allowing simultaneous transmission and reception.
Reserved
Enable CRC Generation
0 The frames placed in the TX FIFO are sent exactly as they are written into the FIFO.
1 Enables the automatic generation of the CRC and its placement at the end of the packet.
Note that this bit should generally be set.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
5 4 3
DUPLEX Reserved
R/W-0 R-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
16
2 1 0
CRC PADEN TXEN
R/W-0 R/W-0 R/W-0
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