Uart Irda Low-Power Register (Uartilpr); Uart Integer Baud-Rate Divisor Register (Uartibrd); Uart Irda Low-Power Register (Uartilpr) Field Descriptions; Uart Integer Baud-Rate Divisor (Uartibrd) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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21.7.4 UART IrDA Low-Power Register (UARTILPR), offset 0x020
The UARTILPR register stores the 8-bit low-power counter divisor value used to derive the low-power SIR
pulse width clock by dividing down the system clock (SysClk). All the bits are cleared when reset.
The internal IrLPBaud16 clock is generated by dividing down SysClk according to the low-power divisor
value written to UARTILPR. The duration of SIR pulses generated when low-power mode is enabled is
three times the period of the IrLPBaud16 clock. The low-power divisor value is calculated as follows:
ILPDVSR = SysClk / F
where F is nominally 1.8432 MHz.
IrLPBaud16
The divisor must be programmed such that 1.42 MHz < F
pulse duration of 1.41-2.11 µs (three times the period of IrLPBaud16). The minimum frequency of
IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but pulses greater than
1.4 µs are accepted as valid pulses.
NOTE: Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being
generated.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21-6. UART IrDA Low-Power Register (UARTILPR) Field Descriptions
Bit Field
31-8 Reserved
7-0 ILPDVSR
21.7.5 UART Integer Baud-Rate Divisor Register (UARTIBRD), offset 0x024
The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared on reset.
The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD register is
ignored. When changing the UARTIBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be
followed by a write to the UARTLCRH register. See
Figure 21-12. UART Integer Baud-Rate Divisor Register (UARTIBRD)
31
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21-7. UART Integer Baud-Rate Divisor (UARTIBRD) Register Field Descriptions
Bit Field
31-16 Reserved
15-0 DIVINT
SPRUHE8E – October 2012 – Revised November 2019
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IrLPBaud16
Figure 21-11. UART IrDA Low-Power Register (UARTILPR)
Reseved
R-0
Value Description
Reserved
IrDA Low-Power Divisor
This field contains the 8-bit low-power divisor value.
R-0
Value Description
Reserved
Integer Baud-Rate Divisor
Copyright © 2012–2019, Texas Instruments Incorporated
< 2.12 MHz, resulting in a low-power
IrLPBaud16
Section 21.3.2 for configuration details.
16 15
M3 Universal Asynchronous Receivers/Transmitters (UARTs)
Register Descriptions
8 7
ILPDVSR
R/W-0
DIVINT
R/W-0
0
0
1503