Message Ram Representation In Debug Mode; Can Control Registers - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Message RAM
Table 23-3. Message RAM Addressing in Debug Mode (continued)
Message Object Number
31

23.14.3 Message RAM Representation in Debug Mode

In debug mode, the Message RAM will be memory mapped. This allows the external debug unit to access
the Message RAM.
NOTE: During debug mode, the Message RAM cannot be accessed via the IFx register sets.
31/ 30/ 29/ 28/
15 14 13 12
MsgAddr + 0x00
MsgAddr + 0x04
MXtd MDir Rsvd
MsgAddr + 0x08
Rsvd Xtd Dir
MsgAddr + 0x0C
MsgLs
Rsvd Rsvd UMask
t
MsgAddr + 0x10
MsgAddr + 0x14

23.15 CAN Control Registers

The base address for the CAN0 registers is 0x4007 0000 and the base address for the CAN1 registers is
0x4007 4000.
Offset
0x00
0x04
0x08
0x0C
0x10
1580
M3 Controller Area Network (CAN)
Offset From Base
Address
0x03E0
0x03E4
0x03E8
0x03EC
0x03F0
0x03F4
Figure 23-18. Message RAM Representation in Debug Mode
27/ 26/ 25/
11 10 9
Reserved
TxIE RxIE RmtEn Rsvd
Data 3
Data 1
Data 7
Data 5
Table 23-4. CAN Control Registers
Acronym Register Description
CAN CTL CAN Control Register
CAN ES Error and Status Register
CAN ERRC Error Counter Register
CAN BTR Bit Timing Register
CAN INT Interrupt Register
Copyright © 2012–2019, Texas Instruments Incorporated
Word Number
1
2
3
4
5
6
24/ 23/ 22/ 21/
8 7 6 5
Reserved
Msk[28:16]
Msk[15:0]
ID[28:16]
ID[15:0]
Reserved
EOB Reserved
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
(1)
Debug Mode
Parity
MXtd,MDir,Mask
Xtd,Dir,ID
Ctrl
Data Bytes 3-0
Data Bytes 7-4
20/ 19/ 18/ 17/
4 3 2 1
Parity[4:0]
DLC[3:0]
Data 2
Data 0
Data 6
Data 4
See
Section 23.15.1
Section 23.15.2
Section 23.15.3
Section 23.15.4
Section 23.15.5
Submit Documentation Feedback
16/
0