Ssiicr Register; Ssiicr Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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20.5.2.9 SSIICR Register (Offset = 20h) [reset = 0h]

SSIICR is shown in

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SSI Interrupt Clear

SPRUHE8E – October 2012 – Revised November 2019

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Figure 20-18

and described in

Figure 20-18. SSIICR Register

Table 20-12. SSIICR Register Field Descriptions

End of Transmit Interrupt Clear

Writing a 1 to this bit clears the EOTRIS bit in the SSIRIS register

and the EOTMIS bit in the SSIMIS register.

Reset type: PER.RESET

SSI Transmit DMA Interrupt Clear

Writing a 1 to this bit clears the DMATXRIS bit in the SSIRIS register

and the DMATXMIS bit in the SSIMIS register.

Reset type: PER.RESET

SSI Receive DMA Interrupt Clear

Writing a 1 to this bit clears the DMARXRIS bit in the SSIRIS register

and the DMARXMIS bit in the SSIMIS register.

Reset type: PER.RESET

SSI Receive Time-Out Interrupt Clear

Writing a 1 to this bit clears the RTRIS bit in the SSIRIS register and

the RTMIS bit in the SSIMIS register.

Reset type: PER.RESET

SSI Receive Overrun Interrupt Clear

Writing a 1 to this bit clears the RORRIS bit in the SSIRIS register

and the RORMIS bit in the SSIMIS register.

Reset type: PER.RESET

M3 Synchronous Serial Interface (SSI)

SSI Registers

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