Gpio Port D Mux 2 (Gpdmux2) Register; Gpio Port D Mux 2 (Gpdmux2) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

www.ti.com
Table 4-57. GPIO Port D MUX 1 (GPDMUX1) Register Field Descriptions (continued)
Bit Field
5-4 GPIO98
3-2 GPIO97
1-0 GPIO96
4.2.7.8

GPIO Port D MUX 2 (GPDMUX2) Register

The GPIO Port D MUX 2 (GPDMUX2) register is shown and described in the figure and table below.
31 30
GPIO127
R/W-0
23 22
GPIO123
R/W-0
15 14
GPIO119
R/W-0
7 6
GPIO115
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-58. GPIO Port D MUX 2 (GPDMUX2) Register Field Descriptions
Bit Field
31-30 GPIO127
29-28 GPIO126
SPRUHE8E – October 2012 – Revised November 2019
Submit Documentation Feedback
Value Description
Configure this pin as:
00 GPIO 98 - general purpose I/O 98 GPIO (default)
01 Reserved
10 Reserved
11 Reserved
Configure this pin as:
00 GPIO 97 - general purpose I/O 97 GPIO (default)
01 Reserved
10 MFSRA
11 Reserved
Configure this pin as:
00 GPIO 96 - general purpose I/O 96 GPIO (default)
01 Reserved
10 MCLKRA
11 Reserved
Figure 4-49. GPIO Port D MUX 2 (GPDMUX2) Register
29 28
GPIO126
R/W-0
21 20
GPIO122
R/W-0
13 12
GPIO118
R/W-0
5 4
GPIO114
R/W-0
Value Description
Configure this pin as:
00 GPIO 127 - general purpose I/O 127 GPIO (default)
01 EPWM8B
10 Reserved
11 Reserved
Configure this pin as:
00 GPIO 126 - general purpose I/O 126 GPIO (default)
01 EPWM8A
10 Reserved
11 Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
C28 General-Purpose Input/Output (GPIO)
27 26
GPIO125
R/W-0
19 18
GPIO121
R/W-0
11 10
GPIO117
R/W-0
3 2
GPIO113
R/W-0
General-Purpose Input/Output (GPIO)
25 24
GPIO124
R/W-0
17 16
GPIO120
R/W-0
9 8
GPIO116
R/W-0
1 0
GPIO112
R/W-0
417