Adcinx Input Model; Sample Timings With Different Values Of Acqps - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Analog-to-Digital Converter (ADC)

TRIGxSEL Bits

10.3.3.1 ADC Acquisition (Sample and Hold) Window

External drivers vary in their ability to drive an analog signal quickly and effectively. Some circuits require

longer times to properly transfer the charge into the sampling capacitor of an ADC. To address this, the

ADC supports control over the sample window length for each individual SOC configuration. Each

ADCSOCxCTL register has a 6-bit field, ACQPS, that determines the sample and hold (S/H) window size.

The value written to this field is one less than the number of cycles desired for the sampling window for

that SOC. Thus, a value of 15 in this field will give 16 clock cycles of sample time. The minimum number

of sample cycles allowed is 7 (ACQPS=6). The total sampling time is found by adding the sample window

size to the conversion time of the ADC, 13 ADC clocks. Examples of various sample times are shown

The total times are for a single conversion and do not include pipelining effects that increase the average speed over time.

Figure 10-12

ground, a voltage swing from 0 to 3.3v on ADCIN yields a typical RC time constant of 2ns.

Typical Values of the Input Circuit Components:

Switch Resistance (R ): 3.4 k

Sampling Capacitor (C ): 1.6 pF

Parasitic Capacitance (C ): 5 pF

Source Resistance (R ): 50

Analog Subsystem

Table 10-2. TRIGxSEL Trigger Options (continued)

Table 10-3. Sample timings with different values of ACQPS

Sample Window

, the ADCIN pins can be modeled as an RC circuit. With VREFLO connected to

Figure 10-12. ADCINx Input Model

Trigger Source

Conversion Time (13

SPRUHE8E – October 2012 – Revised November 2019

Total Time to Process

Analog Voltage

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